參數(shù)資料
型號: DS2152LN
英文描述: Enhanced T1 Single-Chip Transceiver
中文描述: 增強型T1單芯片收發(fā)器
文件頁數(shù): 21/94頁
文件大?。?/td> 1003K
代理商: DS2152LN
DS2152
21 of 93
TCR2: TRANSMIT CONTROL REGISTER 2
(Address=36 Hex)
(MSB) (LSB)
TEST1
TEST0
TZBTSI
TSDW
TSM
TSIO
TD4YM
TB7ZS
SYMBOL
POSITION
NAME AND DESCRIPTION
TEST1
TCR2.7
Test Mode Bit 1 for Output Pins.
See Table 3-1.
TEST0
TCR2.6
Test Mode Bit 0 for Output Pins.
See Table 3-1.
TZBTSI
TCR2.5
Transmit Side ZBTSI Enable.
0 = ZBTSI disabled
1 = ZBTSI enabled
TSDW
TCR2.4
TSYNC Double-Wide.
(note: this bit must be set to 0 when
TCR2.3=1 or when TCR2.2=0)
0 = do not pulse double-wide in signaling frames
1 = do pulse double-wide in signaling frames
TSM
TCR2.3
TSYNC Mode Select.
0 = frame mode (see the timing in Section 15)
1 = multiframe mode (see the timing in Section 15)
TSIO
TCR2.2
TSYNC I/O Select.
0 = TSYNC is an input
1 = TSYNC is an output
TD4YM
TCR2.1
Transmit Side D4 Yellow Alarm Select.
0 = 0s in bit 2 of all channels
1 = a 1 in the S-bit position of frame 12
TB7ZS
TCR2.0
Transmit Side Bit 7 0 Suppression Enable.
0 = no stuffing occurs
1 = Bit 7 force to a 1 in channels with all 0s
OUTPUT PIN TEST MODES
Table 3-1
TEST 1
TEST 0
0
0
0
1
1
0
1
1
EFFECT ON OUTPUT PINS
operate normally
force all output pins 3-state (including all I/O pins and parallel port pins)
force all output pins low (including all I/O pins except parallel port pins)
force all output pins high (including all I/O pins except parallel port pins)
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