參數(shù)資料
型號: DS2152L
英文描述: Enhanced T1 Single-Chip Transceiver
中文描述: 增強型T1單芯片收發(fā)器
文件頁數(shù): 12/94頁
文件大?。?/td> 1003K
代理商: DS2152L
DS2152
12 of 93
Receive Positive Data Output [RPOSO].
Updated on the rising edge of RCLKO with the bipolar data
out of the line interface. This pin is normally tied to RPOSI.
Receive Negative Data Output [RNEGO].
Updated on the rising edge of RCLKO with the bipolar data
out of the line interface. This pin is normally tied to RNEGI.
Receive Clock Output [RCLKO].
Buffered recovered clock from the T1 line. This pin is normally tied
to RCLKI.
Receive Positive Data Input [RPOSI].
Sampled on the falling edge of RCLKI for data to be clocked
through the receive side framer. RPOSI and RNEGI can be tied together for a NRZ interface. Can be
internally connected to RPOSO by tying the LIUC pin high.
Receive Negative Data Input [RNEGI].
Sampled on the falling edge of RCLKI for data to be clocked
through the receive side framer. RPOSI and RNEGI can be tied together for a NRZ interface. Can be
internally connected to RNEGO by tying the LIUC pin high.
Receive Clock Input [RCLKI].
Clock used to clock data through the receive side framer. This pin is
normally tied to RCLKO. Can be internally connected to RCLKO by tying the LIUC pin high.
PARALLEL CONTROL PORT PINS
Interrupt [INT].
Flags host controller during conditions and change of conditions defined in the Status
Registers 1 and 2 and the FDL Status Register. Active low, open drain output.
3-State Control [Test].
Set high to 3-state all output and I/O pins (including the parallel control port). Set
low for normal operation. Useful in board-level testing.
Bus Operation [MUX].
Set low to select non-multiplexed bus operation. Set high to select multiplexed
bus operation.
Data Bus [D0 to D7] or Address/Data Bus [AD0 to AD7].
In non-multiplexed bus operation (MUX =
0), serves as the data bus. In multiplexed bus operation (MUX = 1), serves as an 8-bit multiplexed
address/data bus.
Address Bus [A0 to A6].
In non-multiplexed bus operation (MUX = 0), serves as the address bus. In
multiplexed bus operation (MUX = 1), these pins are not used and should be tied low.
Bus Type Select [BTS].
Strap high to select Motorola bus timing; strap low to select Intel bus timing.
This pin controls the function of the
RD
(
DS
), ALE(AS), and
WR
(R/
W
) pins. If BTS = 1, then these
pins assume the function listed in parenthesis ().
Read Input [
RD
] (Data Strobe [
DS
]).
RD
and
DS
are active low signals when MUX=1. DS is active
high when MUX = 0. See bus timing diagrams.
Chip Select [
CS
].
Must be low to read or write to the device.
CS
is an active low signal.
A7 or Address Latch Enable [ALE] (Address Strobe [AS]).
In non-multiplexed bus operation (MUX =
0), serves as the upper address bit. In multiplexed bus operation (MUX = 1), serves to demultiplex the bus
on a positive-going edge.
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS2152L+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Enhanced T1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2152L-ES 制造商:DALL 功能描述:
DS2152LN 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2152LN+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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