參數(shù)資料
型號: DS21352L
英文描述: 3.3V DS21352 and 5V DS21552 T1 Single-Chip Transceivers
中文描述: 3.3 DS21352及5V DS21552 T1單芯片收發(fā)器
文件頁數(shù): 42/137頁
文件大?。?/td> 1094K
代理商: DS21352L
DS21352/DS21552
42 of 137
CCR7: COMMON CONTROL REGISTER 7 (Address=0A Hex)
(MSB)
LIRST
(LSB)
LIUODO
RLB
RESR
TESR
LIUSI
CDIG
SYMBOL
LIRST
POSITION
CCR7.7
NAME AND DESCRIPTION
Line Interface Reset.
Setting this bit from a zero to a one will initiate an internal reset
that affects the clock recovery state machine and jitter attenuator. Normally this bit is
only toggled on power–up. Must be cleared and set again for a subsequent reset.
Remote Loopback.
0 = loopback disabled
1 = loopback enabled
Receive Elastic Store Reset.
Setting this bit from a zero to a one will minimize the
delay through the receive elastic store. Should be toggled after RSYSCLK has been
applied and is stable. See section 14.3 for details. Do not leave this bit set HIGH.
Transmit Elastic Store Reset.
Setting this bit from a zero to a one will maximize the
delay through the transmit elastic store. Transmit data is lost during the reset. Should be
toggled after TSYSCLK has been applied and is stable. See section 14.3for details. Do
not leave this bit set HIGH.
Reserved.
Must be set low for proper operation.
RLB
CCR7.6
RESR
CCR7.5
TESR
CCR7.4
-
CCR7.3
LIUSI
CCR7.2
Line Interface Synchronization Interface Enable.
This control bit determines whether
the line receiver should handle a normal T1 signal or a 1.544MHz synchronization signal.
This control has no affect on the line interface transmitter.
0 = line receiver configured to support a normal T1 signal
1 = line receiver configured to support a synchronization signal
Customer Disconnect Indication Generator.
This control bit determines whether the
Line Interface will generate an unframed ...1010... pattern at TTIP and TRING instead of
the normal data pattern.
0 = generate normal data at TTIP & TRING as input via TPOSI & TNEGI
1 = generate a ...1010... pattern at TTIP and TRING
Line Interface Open Drain Option.
This control bit determines whether the TTIP and
TRING outputs will be open drain or not. The line driver outputs can be forced open
drain to allow 6Vpeak pulses to be generated or to allow the creation of a very low power
interface.
0 = allow TTIP and TRING to operate normally
1 = force the TTIP and TRING outputs to be open drain
CDIG
CCR7.1
LIUODO
CCR7.0
6.6 REMOTE LOOPBACK
When CCR7.6 is set to a one, the DS21352/552 will be forced into Remote LoopBack (RLB). In this
loopback, data input via the RPOSI and RNEGI pins will be transmitted back to the TPOSO and TNEGO
pins. Data will continue to pass through the receive side framer of the DS21352/552 as it would normally
and the data from the transmit side formatter will be ignored. Please see Figure 3-1 for more details.
相關PDF資料
PDF描述
DS21352LN 3.3V DS21352 and 5V DS21552 T1 Single-Chip Transceivers
DS21552L 3.3V DS21352 and 5V DS21552 T1 Single-Chip Transceivers
DS21552LN 3.3V DS21352 and 5V DS21552 T1 Single-Chip Transceivers
DS21354 MTTF is frequently used interchangeably with MTBF
DS21354L 3.3V/5V E1 Single-Chip Transceivers
相關代理商/技術參數(shù)
參數(shù)描述
DS21352L+ 功能描述:網(wǎng)絡控制器與處理器 IC T1 Single Chip Transceivers RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21352LB 功能描述:網(wǎng)絡控制器與處理器 IC T1 Single Chip Transceivers RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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