參數(shù)資料
型號： DS21348GN
英文描述： 3.3V E1/T1/J1 Line Interface
中文描述： 3.3 E1/T1/J1線路接口
文件頁數(shù)： 17/73頁
文件大小： 551K
代理商： DS21348GN
DS21348/Q348
17 of 73
PIN DESCRIPTIONS IN HARDWARE MODE
(Sorted by Pin Name, DS21348T Pin
Numbering)
Table 4-4b
ACRONYM
PIN
I/O
DESCRIPTION
BIS0/
BIS1
BPCLK
32/
33
31
I
Bus Interface Select Bits 0 & 1.
Used to select bus interface option.
See Table 4-1 for details.
Back Plane Clock.
A 16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz clock output that is referenced to RCLK selectable via
CCR5.7 and CCR5.6. In hardware mode, defaults to 16.384MHz
output.
Receive & Transmit Clock Edge Select.
Selects which RCLK
edge to update RPOS and RNEG and which TCLK edge to sample
TPOS and TNEG. CES combines TCES (CCR2.1) and RCES
(CCR2.0).
0 = update RNEG/RPOS on rising edge of RCLK; sample
TPOS/TNEG on falling edge of TCLK
1 = update RNEG/RPOS on falling edge of RCLK; sample
TPOS/TNEG on rising edge of TCLK
Disable Jitter Attenuator.
0 = jitter attenuator enabled
1 = jitter attenuator disabled
Receive Equalizer Gain Limit.
This bit controls the sensitivity of
the receive equalizer. See Table 4-7.
E1/T1 Select.
0 = E1
1 = T1
Receive & Transmit HDB3/B8ZS Enable.
HBE combines RHBE
(CCR2.3) and THBE (CCR2.2).
0 = enable HDB3 (E1)/B8ZS (T1)
1 = disable HDB3 (E1)/B8ZS (T1)
Hardware Reset.
Bringing HRST* low will reset the DS21348
setting all control bits to their default state of all zeros.
Jitter Attenuator MUX.
Controls the source for JACLK. See
Figure 3-1 and Table 4-10.
0 = JACLK sourced from MCLK (2.048MHz or 1.544MHz at
MCLK)
1 = JACLK sourced from internal PLL (2.048MHz at MCLK)
Jitter Attenuator Select.
0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
Transmit LIU Waveshape Select Bits 0 & 1 [H/W Mode].
These
inputs determine the waveshape of the transmitter. See Table 9-1
and Table 9-2.
Loopback Select Bits 0 & 1 [H/W Mode].
These inputs determine
the active loopback mode (if any). See Table 4-5.
O
CES
12
I
DJA
8
I
EGL
1
I
ETS
2
I
HBE
11
I
HRST*
29
I
JAMUX
9
I
JAS
10
I
L0/L1/L2
7/
6/
5
16/
17
I
LOOP0/
LOOP1
I
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相關代理商/技術參數(shù)
參數(shù)描述
DS21348GN+ 功能描述:網(wǎng)絡控制器與處理器 IC 3.3V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21348GNB 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21348GN-C01 功能描述:網(wǎng)絡控制器與處理器 IC 3.3V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21348T 功能描述:網(wǎng)絡控制器與處理器 IC 3.3V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21348T+ 功能描述:網(wǎng)絡控制器與處理器 IC 3.3V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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