參數(shù)資料
型號(hào)： DS21348GN
英文描述： 3.3V E1/T1/J1 Line Interface
中文描述： 3.3 E1/T1/J1線路接口
文件頁數(shù)： 14/73頁
文件大?。?/td> 551K
代理商： DS21348GN
DS21348/Q348
14 of 73
DS21348T
PIN #
40
41
42
43
44
DS21348G
PIN#
B3
A3
B2
A2
A1
I/O
Serial
Port Mode
RCLK
TPOS
TNEG
TCLK
NA
O
I
I
I
I
PIN DESCRIPTIONS IN SERIAL PORT MODE
(Sorted by Pin Name, DS21348T
Pin Numbering)
Table 4-3b
ACRONYM
PIN
I/O
DESCRIPTION
BIS0/
BIS1
BPCLK
32/
33
31
I
Bus Interface Select Bits 0 & 1.
Used to select bus interface option.
See Table 4-1 for details.
Back Plane Clock.
A 16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz clock output that is referenced to RCLK selectable via
CCR5.7 and CCR5.6. In hardware mode, defaults to 16.384 MHz
output.
Chip Select.
Must be low to read or write to the device. CS* is an
active low signal.
Hardware Reset.
Bringing HRST* low will reset the DS21348
setting all control bits to their default state of all zeros.
Input Clock Edge Select.
Selects whether the serial port data input
(SDI) is sampled on rising (ICES =0) or falling edge (ICES = 1) of
SCLK.
Interrupt [INT*] Pin 23.
Flags host controller during conditions
and change of conditions defined in the Status Register. Active low,
open drain output.
Master Clock.
A 2.048MHz (±50ppm) clock source with TTL
levels is applied at this pin. This clock is used internally for both
clock/data recovery and for jitter attenuation. Use of a T1 1.544
MHz clock source is optional.
See Note 2.
Not Assigned.
Should be tied low.
Output Clock Edge Select.
Selects whether the serial port data
output (SDO) is valid on the rising (OCES = 1) or falling edge
(OCES = 0) of SCLK.
PRBS Bit Error Output.
The receiver will constantly search for a
2
15
-1 or a 2
20
-1 PRBS depending on the ETS bit setting (CCR1.7).
Remains high if out of synchronization with the PRBS pattern. Goes
low when synchronized to the PRBS pattern. Any errors in the
received pattern after synchronization will cause a positive going
pulse (with same period as E1 or T1 clock) synchronous with
RCLK. PRBS bit errors can also be reported to the ECR1 and ECR2
registers by setting CCR6.2 to a logic 1.
Receive Clock.
Buffered recovered clock from the line.
Synchronous to MCLK in absence of signal at RTIP and RRING.
O
CS*
1
I
HRST*
29
I
ICES
8
I
INT*
23
O
MCLK
30
I
NA
OCES
-
9
I
I
PBEO
24
O
RCLK
40
O
相關(guān)PDF資料
PDF描述
DS21348 3.3V E1/T1/J1 Line Interface
DS21348T 3.3V E1/T1/J1 Line Interface
DS21348TN 3.3V E1/T1/J1 Line Interface
DS21352 3.3V DS21352 and 5V DS21552 T1 Single-Chip Transceivers
DS21352L 3.3V DS21352 and 5V DS21552 T1 Single-Chip Transceivers
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS21348GN+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21348GNB 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21348GN-C01 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21348T 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21348T+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*