參數(shù)資料
型號: DS1825U+T&R
廠商: Maxim Integrated
文件頁數(shù): 17/21頁
文件大小: 287K
描述: IC THERMOMETER DIGITAL 8-USOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 3,000
功能: 溫度計,恒溫計
傳感器類型: 內(nèi)部
感應(yīng)溫度: -55°C ~ 125°C
精確度: ±2°C(最小值)
拓?fù)洌?/td> 寄存器庫,變簽式暫存器
輸出類型: 數(shù)字
輸出警報:
輸出風(fēng)扇:
電源電壓: 3 V ~ 3.7 V
工作溫度: -55°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-uMAX
包裝: 帶卷 (TR)
DS1825 Programmable Resolution 1-Wire Digital Thermometer With 4-Bit ID
 
17 of 21
 
 
Figure 15. READ/WRITE TIME SLOT TIMING DIAGRAM  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
READ TIME SLOTS
The DS1825 can only transmit data to the master when the master issues read time slots. Therefore, the master
must generate read time slots immediately after issuing a Read Scratchpad [BEh] or Read Power Supply [B4h]
command, so that the DS1825 can provide the requested data. In addition, the master can generate read time slots
after issuing Convert T [44h] or Recall E
2
 [B8h] commands to find out the status of the operation as explained in
the DS1825 FUNCTION COMMAND section.
 
All read time slots must be a minimum of 60ms in duration with a minimum of a 1ms recovery time between slots. A
read time slot is initiated by the master device pulling the 1-Wire bus low for a minimum of 1ms and then releasing
the bus (see Figure 14). After the master initiates the read time slot, the DS1825 will begin transmitting a 1 or 0 on
bus. The DS1825 transmits a 1 by leaving the bus high and transmits a 0 by pulling the bus low. When transmitting
a 0, the DS1825 will release the bus by the end of the time slot, and the bus will be pulled back to its high idle state
by the pullup resister. Output data from the DS1825 is valid for 15ms after the falling edge that initiated the read
time slot. Therefore, the master must release the bus and then sample the bus state within 15ms from the start of
the slot. 
Figure 15 illustrates that the sum of T
INIT
, T
RC
, and T
SAMPLE
 must be less than 15ms for a read time slot. Figure 16
shows that system timing margin is maximized by keeping T
INIT
 and T
RC
 as short as possible and by locating the
master sample time during read time slots towards the end of the 15ms period.
45 ms
15 ms
V
PU
 
GND
1-WIRE BUS
60 ms < T
X
 0 < 120 ms
1 ms < T
REC
 < ?/SPAN>
DS1825 Samples
MIN TYP MAX
15 ms
30 ms
> 1 ms
MASTER WRITE 0 SLOT
MASTER WRITE 1 SLOT 
V
PU
 
GND
1-WIRE BUS
15 ms
MASTER READ 0 SLOT
MASTER READ 1 SLOT 
Master samples
Master samples 
START
OF SLOT 
START
OF SLOT
> 1 ms
1 ms < T
REC
 < ?/SPAN>
15 ms
15 ms
30 ms
15 ms
DS1825 Samples
MIN TYP MA
LINE TYPE LEGEND
Bus master pulling low
 
DS1825 pulling low
 
 
Resistor pullup
> 1 ms 
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