參數(shù)資料
型號(hào)： DS17485E-5
廠商： DALLAS SEMICONDUCTOR
元件分類： Timer or RTC
英文描述： 1 TIMER(S), REAL TIME CLOCK, PDSO28
封裝： TSOP-28
文件頁(yè)數(shù)： 14/38頁(yè)
文件大?。?/td> 400K
代理商： DS17485E-5
DS17485/DS17487
21 of 38
EXTENDED CONTROL REGISTERS
Two extended control registers are provided to supply controls and status information for the extended
features offered by the DS17485/DS17487. These are designated as extended control registers 4A and
4B and are located in register bank 1, locations 04AH and 04BH, respectively. The functions of the bits
within these registers are described as follows.
EXTENDED CONTROL REGISTER 4A
MSB
LSB
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
VRT2
INCR
BME
*
PAB
RF
WF
KF
VRT2 – The valid RAM and Time 2 bit is a read-only status bit. When VRT2=0, the RTC and RAM
data are questionable and indicates that the lithium energy source connected to the VBAUX input has been
exhausted and should be replaced. This bit indicates the status of the VBAUX input.
INCR - Increment in Progress status bit. This bit is set to a 1 when an increment to the time/date
registers is in progress and the alarm checks are being made. INCR will be set to a 1 at 122 s before the
update cycle starts and will be cleared to 0 at the end of each update cycle.
BME - Burst Mode Enable. The burst mode enable bit allows the extended user RAM address registers
to automatically increment for consecutive reads and writes. When BME is set to a logic 1, the automatic
incrementing will be enabled and when BME is set to a logic 0, the automatic incrementing will be
disabled.
PAB - Power Active Bar control bit. When this bit is 0, the PWR pin is in the active low state. When
this bit is 1, the PWR pin is in the high impedance state. This bit can be written to a logic 1 or 0 by the
User. If either WF AND WIE = 1 OR KF AND KSE = 1, the PAB bit will be cleared to 0.
RF - Ram Clear Flag. This bit will be set to a logic 1 when a high to low transition occurs on the RCLR
input if RCE=1. The RF bit is cleared by writing it to a logic 0. This bit can also be written to a logic 1
to force an interrupt condition.
WF - Wake-up Alarm Flag - This bit is set to 1 when a wake-up alarm condition occurs or when the User
writes it to a 1. WF is cleared by writing it to a 0.
KF - Kickstart Flag - This bit is set to a 1 when a kickstart condition occurs or when the User writes it to
a 1. This bit is cleared by writing it to a logic 0.
* Reserved bits. These bits are reserved for future use by Dallas Semiconductor. They can be read and
written, but have no effect on operation.
相關(guān)PDF資料
PDF描述
DS17485-3 1 TIMER(S), REAL TIME CLOCK, PDIP24
DS17485-5 1 TIMER(S), REAL TIME CLOCK, PDIP24
DS17485S-3 1 TIMER(S), REAL TIME CLOCK, PDSO24
DS17485S-5 1 TIMER(S), REAL TIME CLOCK, PDSO24
DS17485E-3 1 TIMER(S), REAL TIME CLOCK, PDSO28
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS17485E-5+ 功能描述:實(shí)時(shí)時(shí)鐘 3V/5V RTC RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube
DS17485EN-3 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3V/5V Real-Time Clock
DS17485EN-5 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3V/5V Real-Time Clock
DS17485N-3 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Real-Time Clock
DS17485N-5 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Real-Time Clock
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