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參數(shù)資料
| 型號： | DS1342U+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 15/16頁 |
| 文件大小： | 0K |
| 描述： | IC RTC I2C W/ALARM 8USOP |
| 產(chǎn)品培訓模塊： | DS134x Real Time Clocks Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1 |
| 類型： | 時鐘/日歷 |
| 特點： | 警報器，閏年，方波輸出 |
| 時間格式： | HH:MM:SS（12/24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 1.8 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 8-uMAX |
| 包裝： | 標準包裝 |
| 其它名稱： | DS1342U+T&RDKR |
8
Maxim Integrated
Low-Current I2C RTCs for High-ESR Crystals
DS1341/DS1342
External Synchronization
When an external clock reference is used, the input
from CLKIN/INTA is divided down to 1Hz by the divi-
sor selected by the CLKSEL[2:1] bits. The 1Hz from the
divider (Ext-1Hz, see the Functional Diagram) is used to
correct the 1Hz that is derived from the 32.768kHz oscil-
lator (Osc-1Hz). As Osc-1Hz drifts in relation to Ext-1Hz,
Osc-1Hz is digitally adjusted.
As shown in the Functional Diagram, the three highest
frequencies driving the SQW/INTB pin are derived from
the uncorrected oscillator, while the 1Hz output is derived
from the adjusted Osc-1Hz signal.
Conceptually, the circuit can be thought of as two 1Hz
signals, one derived from the internal oscillator and the
other derived from the external reference clock, with the
oscillator-derived 1Hz signal being locked to the 1Hz sig-
nal derived from the external reference clock. The edges
of the 1Hz signals do not need to be aligned with each
other. While the external clock source is present and
within tolerance, the Ext-1Hz and Osc-1Hz maintain their
existing lock, regardless of their edge alignment, with
periodic correction of the Osc-1Hz signal. If the external
signal is lost and then regained sometime later, the sig-
nals relock with whatever new alignment exists (Figure 3).
The Ext-1Hz is used by the device as long as it is within
tolerance, which is about 0.8% of Osc-1Hz. While Ext-
1Hz is within tolerance, the skew between the two sig-
nals could shift until a change of approximately 7.8ms
accumulates, after which the Osc-1Hz signal is adjusted
(Figure 4). The adjustment is accomplished by digitally
adjusting the 32kHz oscillator divider chain.
If the difference between Ext-1Hz and Osc-1Hz is greater
than approximately 0.8%, Osc-1Hz runs unadjusted (see
Figure 3) and the loss of signal (LOS) is set, provided
Figure 3. Loss and Reacquisition of External Reference Clock
Figure 4. Drift and Adjustment of Internal 1Hz to External Reference Clock
OSC-1Hz
FROM OSCILLATOR
EXT-1Hz
FROM EXTERNAL REFERENCE
SKEW
BREAK IN EXTERNAL REFERENCE SIGNAL
CURRENT LOCK
SHIFTED BACK TO CURRENT LOCK
DRIFT AFTER N CYCLES
OSC-1Hz
FROM OSCILLATOR
EXT-1Hz
FROM EXTERNAL REFERENCE
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參數(shù)描述 |
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