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參數資料
| 型號： | DS1342U+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數： | 10/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC I2C W/ALARM 8USOP |
| 產品培訓模塊： | DS134x Real Time Clocks Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1 |
| 類型： | 時鐘/日歷 |
| 特點： | 警報器，閏年，方波輸出 |
| 時間格式： | HH:MM:SS（12/24 小時） |
| 數據格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 1.8 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 8-uMAX |
| 包裝： | 標準包裝 |
| 其它名稱： | DS1342U+T&RDKR |
3
Maxim Integrated
Low-Current I2C RTCs for High-ESR Crystals
DS1341/DS1342
AC ELECTRICAL CHARACTERISTICS
(VCC = +1.8V to +5.5V, TA = -40NC to +85NC, unless otherwise noted.) (Note 2, Figure 1)
CRYSTAL PARAMETERS
Note 2:
Limits at -40NC are guaranteed by design; not production tested.
Note 3:
Voltage referenced to ground.
Note 4:
Specified with I2C bus inactive. Oscillator operational, INTCN = 1, ECLK = 0.
Note 5:
Applies to CLKIN/INTA and SQW/INTB only.
Note 6:
The minimum SCL clock frequency is limited by the bus timeout feature, which resets the serial bus interface if SCL is
held low for tTIMEOUT.
Note 7:
After this period, the first clock pulse is generated.
Note 8:
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCL sig-
nal) to bridge the undefined region of the falling edge of SCL.
Note 9:
The maximum tHD:DAT need only be met if the device does not stretch the low period (tLOW) of the SCL signal.
Note 10: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT R to 250ns must then be
met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does
stretch the low period of the SCL signal, it must output the next data bit to the SDA line tRMAX + tSU:DAT = 1000 + 250 =
1250ns before the SCL line is released.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCL Clock Frequency
fSCL
(Note 6)
400
kHz
Bus Free Time Between a STOP
and START Condition
tBUF
1.3
F
s
Hold Time (Repeated) START
Condition
tHD:STA
(Note 7)
0.6
F
s
Low Period of SCL Clock
tLOW
1.3
F
s
High Period of SCL Clock
tHIGH
0.6
F
s
Data Hold Time
tHD:DAT
(Notes 8, 9)
0
0.9
F
s
Data Setup Time
tSU:DAT
(Note 10)
100
ns
Setup Time for a Repeated
START Condition
tSU:STA
0.6
F
s
Rise Time of Both SDA and SCL
Signals
tR
(Note 11)
20 +
0.1CB
300
ns
Fall Time for Both SDA and SCL
Signals
tF
(Note 11)
20 +
0.1CB
300
ns
Setup Time for STOP Condition
tSU:STO
0.6
F
s
Capacitive Load for Each Bus
Line
CB
(Note 11)
400
pF
I/O Capacitance
CI/O
(Note 12)
10
pF
SCL Spike Suppression
tSP
(Note 12)
30
ns
Oscillator Stop Flag (OSF) Delay
tOSF
(Note 13)
25
100
ms
Timeout Interval
tTIMEOUT (Note 14)
25
35
ms
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Nominal Frequency
fO
32.768
kHz
Series Resistance
ESR
100
kI
Load Capacitance
CL
DS1341
6
pF
DS1342
12.5
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