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參數(shù)資料
| 型號： | DS12R885S-5+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 9/23頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC W/RAM 128 BYTE 24-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 時(shí)鐘/日歷 |
| 特點(diǎn)： | 警報(bào)器，閏年，NVSRAM，方波輸出，涓流充電器 |
| 存儲容量： | 114B |
| 時(shí)間格式： | HH:MM:SS（12/24 小時(shí)） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | 并聯(lián) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 電壓 - 電源，電池： | 2 V ~ 3.05 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SOIC W |
| 包裝： | 帶卷 (TR) |
DS12R885/DS12CR887/DS12R887
17
Maxim Integrated
Bit 7: SET. When the SET bit is 0, the update transfer
functions normally by advancing the counts once per
second. When the SET bit is written to 1, any update
transfer is inhibited, and the program can initialize the
time and calendar bytes without an update occurring in
the midst of initializing. Read cycles can be executed in
a similar manner. SET is a read/write bit and is not
affected by RESET or internal functions of the
DS12R885.
Bit 6: Periodic Interrupt Enable (PIE). The PIE bit is a
read/write bit that allows the periodic interrupt flag (PF) bit
in Register C to drive the IRQ pin low. When the PIE bit is
set to 1, periodic interrupts are generated by driving the
IRQ pin low at a rate specified by the RS3–RS0 bits of
Register A. A 0 in the PIE bit blocks the IRQ output from
being driven by a periodic interrupt, but the PF bit is still
set at the periodic rate. PIE is not modified by any internal
DS12R885 functions, but is cleared to 0 on RESET.
Bit 5: Alarm Interrupt Enable (AIE). This bit is a
read/write bit that, when set to 1, permits the alarm flag
(AF) bit in Register C to assert IRQ. An alarm interrupt
occurs for each second that the three time bytes equal
the three alarm bytes, including a don’t-care alarm
code of binary 11XXXXXX. The AF bit does not initiate
the IRQ signal when the AIE bit is set to 0. The internal
functions of the DS12R885 do not affect the AIE bit, but
is cleared to 0 on RESET.
Bit 4: Update-Ended Interrupt Enable (UIE). This bit is
a read/write bit that enables the update-end flag (UF)
bit in Register C to assert IRQ. The RESET pin going
low or the SET bit going high clears the UIE bit. UIE is
not modified by any internal DS12R885 functions, but is
cleared to 0 on RESET.
Bit 3: Square-Wave Enable (SQWE). When this bit is
set to 1, a square-wave signal at the frequency set by
the rate-selection bits RS3–RS0 is driven out on the
SQW pin. When the SQWE bit is set to 0, the SQW pin
is held low. SQWE is a read/write bit and is cleared by
RESET. SQWE is low if disabled, and is high imped-
ance when VCC is below VPF. SQWE is cleared to 0 on
RESET.
Bit 2: Data Mode (DM). This bit indicates whether time
and calendar information is in binary or BCD format.
The DM bit is set by the program to the appropriate for-
mat and can be read as required. This bit is not modi-
fied by internal functions or RESET. A 1 in DM signifies
binary data, while a 0 in DM specifies BCD data.
Bit 1: 24/12. The 24/12 control bit establishes the for-
mat of the hours byte. A 1 indicates the 24-hour mode
and a 0 indicates the 12-hour mode. This bit is
read/write and is not affected by internal functions or
RESET.
Bit 0: Daylight Saving Enable (DSE). This bit is a
read/write bit that enables two daylight saving adjust-
ments when DSE is set to 1. On the first Sunday in
April, the time increments from 1:59:59 AM to 3:00:00
AM. On the last Sunday in October when the time first
reaches 1:59:59 AM, it changes to 1:00:00 AM. When
DSE is enabled, the internal logic tests for the first/last
Sunday condition at midnight. If the DSE bit is not set
when the test occurs, the daylight saving function does
not operate correctly. These adjustments do not occur
when the DSE bit is 0. This bit is not affected by internal
functions or RESET.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SET
PIE
AIE
UIE
SQWE
DM
24/12
DSE
Control Register B
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