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參數(shù)資料
型號(hào)： DS12R885S-5+T&R
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 23/23頁(yè)
文件大?。?/td> 0K
描述： IC RTC W/RAM 128 BYTE 24-SOIC
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1,000
類(lèi)型： 時(shí)鐘/日歷
特點(diǎn)： 警報(bào)器，閏年，NVSRAM，方波輸出，涓流充電器
存儲(chǔ)容量： 114B
時(shí)間格式： HH:MM:SS（12/24 小時(shí)）
數(shù)據(jù)格式： YY-MM-DD-dd
接口： 并聯(lián)
電源電壓： 4.5 V ~ 5.5 V
電壓 - 電源，電池： 2 V ~ 3.05 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 24-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 24-SOIC W
包裝： 帶卷 (TR)
DS12R885/DS12CR887/DS12R887
RTCs with Constant-Voltage Trickle Charger
9
Maxim Integrated
POWER
CONTROL
AND
TRICKLE
CHARGER
VBACKUP
OSC
BUS
INTERFACE
VCC
X1
X2
DS12R887/
DS12CR887
ONLY
DS12R887/
DS12CR887
ONLY
RESET
CS
DS
AS
R/W
MOT
AD0–AD7
DIVIDE
BY 8
DIVIDE
BY 64
DIVIDE
BY 64
16:1 MUX
SQUARE-
WAVE
GENERATOR
REGISTERS A, B, C, D
CLOCK/CALENDAR AND
ALARM REGISTERS
USER RAM
114 BYTES
CLOCK/CALENDAR
UPDATE LOGIC
IRQ
SQW
IRQ
GENERATOR
BUFFERED CLOCK/
CALENDAR AND ALARM
REGISTERS
GND
RLCR
DS12R885
Functional Diagram
Pin Description
PIN
SO
EDIP
BGA
NAME
FUNCTION
1
C5
MOT
Motorola or Intel Bus Timing Selector. This pin selects one of two bus types. When
connected to VCC, Motorola bus timing is selected. When connected to GND or left
disconnected, Intel bus timing is selected. The pin has an internal pulldown resistor.
2
—
X1
3
—
X2
Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator circuitry is
designed for operation with a crystal having a 12.5pF specified load capacitance (CL).
Pin X1 is the input to the oscillator and can optionally be connected to an external
32.768kHz oscillator. The output of the internal oscillator, pin X2, is left unconnected if
an external oscillator is connected to pin X1.
4–11
F4, D4,
F3, D3,
F2, D2,
F1, D1
AD0–
AD7
Multiplexed, Bidirectional Address/Data Bus. The addresses are presented during the first
portion of the bus cycle and latched into the DS12R885 by the falling edge of AS. Write
data is latched by the falling edge of DS (Motorola timing) or the rising edge of R/W (Intel
timing). In a read cycle, the DS12R885 outputs data during the latter portion of DS (DS and
R/W high for Motorola timing, DS low and R/W high for Intel timing). The read cycle is
terminated and the bus returns to a high-impedance state as DS transitions low in the case
of Motorola timing or as DS transitions high in the case of Intel timing.
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