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參數資料
| 型號： | DRX3960A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Digital Receiver Front-end |
| 中文描述： | 數字接收機前端 |
| 文件頁數： | 22/30頁 |
| 文件大?。?/td> | 450K |
| 代理商： | DRX3960A |
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DRX 3960A
ADVANCE INFORMATION
22
Micronas
Pin 37,
ADR_SEL
I
2
C Bus address select
By means of this pin, one of three device addresses
can be selected.
Pin 39,
DVDD_ADC
Digital supply pin for ADC
This pin has to be connected to 3.3 V.
Pin 40,
DVSS_ADC
Digital ground pin for ADC.
This pin has to be connected to digital ground.
Pin 41,
XTAL_IN
Crystal input pin
If an external clock is used this pin should be left open.
A crystal should be placed as close as possible to this
pin. External capacitors at each crystal pin to ground
are required. It should be verified by layout, that no
supply current is flowing through the ground connec-
tion point.
Pin 42,
XTAL_OUT
Crystal output pin
If an external clock is used, it has to be connected to
this pin. A crystal should be placed as close as possi-
ble to this pin. External capacitors at each crystal pin
to ground are required. It should be verified by layout,
that no supply current is flowing through the ground
connection point.
Pin 43,
VREF
Analog reference voltage
This pin must be connected to SGND via a circuitry
according to the application circuit.
Pin 43,
SGND
Reference for analog ground
This pin must be connected separately to a single
ground point.
5.4. Pin Configuration
Fig. 5
–
2:
44-pin PMQFP package
34
35
36
37
38
39
40
41
42
43
44
22
21
20
19
18
17
16
15
14
13
12
1
2
3
4
5
6
7
8
9
10 11
33 32 31 30 29 28 27 26 25 24 23
PORT2
PORT3
PORT4
ADR_SEL
PORT5
DVDD_ADC
DVSS_ADC
XTAL_IN
XTAL_OUT
VREF
SGND
AVSS_DAC
AVDD_DAC
SIF
REF_SW
CVBS
TEST2
TEST1
TEST0
SHIELD
AVSS_SYN
AVDD_SYN
PORT1
PORT0
DVSS_CAP
DVSS
DVDD
TUNER_AGC
DVDD_CAP
I2C_SCL
I2C_SDA
RESETQ
TEST_EN
AVDD_ADC
ANATSTX
ANATSTY
AVDD_FE8
AVSS_FE8
AVSS_ADC
AVSS_FE40
IFINX
AVDD_FE40
IFINY
AVSS_FE40
DRX 3960A
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