參數(shù)資料
型號(hào)： DRX3960A
廠(chǎng)商： Electronic Theatre Controls, Inc.
英文描述： Digital Receiver Front-end
中文描述： 數(shù)字接收機(jī)前端
文件頁(yè)數(shù)： 11/30頁(yè)
文件大小： 450K
代理商： DRX3960A
ADVANCE INFORMATION
DRX 3960A
Micronas
11
4. Control Interface
4.1. I
2
C Bus Interface
4.1.1. Device and Subaddresses
The DRX 3960A is controlled via the I
2
C bus slave
interface.
The IC is selected by transmitting one of the
DRX 3960A device addresses. In order to allow up to
three ICs to be connected to a single bus, an address
select pin (ADR_SEL) has been implemented. With
ADR_SEL pulled to high, low, or left open, the
DRX 3960A responds to different device addresses. A
device address pair is defined as a write address and a
read address.
Writing is done by sending the device write address,
followed by the subaddress byte, two address bytes,
and two data bytes. Reading is done by sending the
write device address, followed by the subaddress byte
and two address bytes. Without sending a stop condi-
tion, reading of the addressed data is completed by
sending the device read address and reading two
bytes of data.
Due to the internal architecture of the DRX 3960A, the
IC cannot react immediately to an I
2
C request. The
typical response time is about 0.3 ms. If the
DRX 3960A cannot accept another complete byte of
data until it has performed some other function (for
example, servicing an internal interrupt), it will hold the
clock line low to force the transmitter into a wait state.
The maximum wait period during normal operation
mode is less than 1 ms.
Table 4
–
1:
I
2
C Bus Device Addresses
ADR_SEL
Low
High
Left Open
Mode
Write
Read
Write
Read
Write
Read
Device address
82
hex
83
hex
86
hex
87
hex
8A
hex
8B
hex
Table 4
–
2:
I
2
C Bus Subaddresses
Name
Binary Value
Hex Value
Mode
Function
CONTROL
0000 0000
00
Read/Write
Write
Read
: Software reset of DRX
: Hardware error status of DRX
PORT
0000 0011
03
Write
output port address
WR_DRX
0001 0000
10
Write
write address
RD_DRX
0001 0001
11
Write
read address
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