參數(shù)資料
型號(hào)： DRX3960A
廠商： Electronic Theatre Controls, Inc.
英文描述： Digital Receiver Front-end
中文描述： 數(shù)字接收機(jī)前端
文件頁數(shù)： 13/30頁
文件大小： 450K
代理商： DRX3960A
ADVANCE INFORMATION
DRX 3960A
Micronas
13
4.1.3. Protocol Description
Write protocol
Read protocol
Write to Control or Test Registers
Write to Port Registers
Note:
S =
I
2
C bus Start Condition from master
I
2
C bus Stop Condition from master
ACK = Acknowledge-Bit: LOW on I2C_DA from slave (= DRX, light gray)
or master (= controller dark gray)
NAK = Not Acknowledge-Bit: HIGH on I2C_DA from master (dark gray) to indicate
‘
End of Read
’
or from DRX indicating internal error state
Wait = I
2
C clock line is held low, while the DRX is processing the I
2
C command. This waiting time is
max. 1 ms
P =
Fig. 4
–
1:
I
2
C bus protocol (MSB first; data must be stable while clock is high)
S
write
device
address
Wait
ACK
sub-addr ACK addr-byte
high
ACK addr-byte
low
ACK data-byte-
high
ACK data-byte
low
ACK
P
S
write
device
address
Wait
ACK
sub-addr ACK addr-byte
high
ACK addr-byte
low
ACK
S
read
device
address
Wait
ACK data-byte-
high
ACK data-byte
low
NAK
P
S
write
device
address
Wait
ACK
sub-addr ACK data-byte
high
ACK data-byte
low
ACK
P
S
write
device
address
Wait
ACK
sub-addr ACK data-byte ACK
P
1
0
S
P
I2C_DA
I2C_CL
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