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參數資料
| 型號： | DR8051XP |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 8位微控制器 |
| 英文描述： | High Performance Configurable 8-bit Microcontroller ver 3.01 |
| 中文描述： | 高性能可配置8位微控制器版本3.01 |
| 文件頁數： | 5/7頁 |
| 文件大?。?/td> | 101K |
| 代理商： | DR8051XP |
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.
microcontroller is planned to use in portable
and power critical applications.
DoCD
Debug Unit
– it’s a real-time hard-
ware debugger provides debugging capability
of a whole SoC system. In contrast to other on-
chip debuggers DoCD provides non-intrusive
debugging of running application. It can halt,
run, step into or skip an instruction, read/write
any contents of microcontroller including all
registers, internal, external, program memo-
ries, all SFRs including user defined peripher-
als. Hardware breakpoints can be set and con-
trolled on program memory, internal and exter-
nal data memories, as well as on SFRs. Hard-
ware breakpoint is executed if any write/read
occurred at particular address with certain data
pattern or without pattern. The DoCD system
includes three-wire interface and complete set
of tools to communicate and work with core in
real time debugging. It is built as scalable unit
and some features can be turned off to save
silicon and reduce power consumption. A spe-
cial care on power consumption has been
taken, and when debugger is not used it is
automatically switched in power save mode.
Finally whole debugger is turned off when de-
bug option is no longer used.
P E R F O R M AN C E
The following tables give a survey about the
Core area and performance in Programmable
Logic Devices after Place & Route (all CPU
features and peripherals have been included):
Device
ORCA 4E
Core performance in LATTICE devices
Speed grade
-3
F
max
50 MHz
For a user the most important is application
speed improvement. The most commonly used
arithmetic functions and their improvements
are shown in table below. An improvement was
computed as {80C51 clock periods} divided by
{DR8051CPU clock periods} required to exe-
cute an identical function. More details are
available in core documentation.
Function
Improvement
7,20
6,00
6,00
7,20
7,20
6,00
6,00
7,20
10,67
9,60
7,20
7,64
9,75
7,20
7,43
9,04
7,58
8-bit addition (
immediate data
)
8-bit addition (
direct addressing
)
8-bit addition (
indirect addressing
)
8-bit addition (
register addressing
)
8-bit subtraction (
immediate data
)
8-bit subtraction (
direct addressing
)
8-bit subtraction (
indirect addressing
)
8-bit subtraction (
register addressing
)
8-bit multiplication
8-bit division
16-bit addition
16-bit subtraction
16-bit multiplication
32-bit addition
32-bit subtraction
32-bit multiplication
Average speed improvement:
Dhrystone Benchmark Version 2.1 was used to
measure Core performance. The following ta-
ble gives a survey about the DR8051CPU per-
formance in terms of Dhrystone/sec and VAX
MIPS rating.
Device
Target
Clock
frequency
12 MHz
33 MHz
40 MHz
Dhry/sec
(VAX MIPS)
268 (0.153)
1550 (0.882)
6452 (3.672)
80C51
80C310
DR8051CPU
-
-
ORCA 4E
Core performance in terms of Dhrystones
268
1550
6452
0
2000
4000
6000
8000
80C51 (12MHz)
80C310 (33MHz)
DR8051CPU (40MHz)
Area utilized by the each unit of DR8051CPU
core in vendor specific technologies is summa-
rized in table below.
Area
Component
[LC/PFU]
1510
[FFs]
220
40
CPU*
Interrupt Controller
Power Management Unit
Total area
*CPU – consisted of ALU, Opcode Decoder, Control Unit, Program &
Internal & External Memory Interfaces, User SFRs Interface
Core components area utilization
110
10
5
1630 / 299
265
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