參數(shù)資料
型號(hào): DR8051XP
廠商: Electronic Theatre Controls, Inc.
元件分類(lèi): 8位微控制器
英文描述: High Performance Configurable 8-bit Microcontroller ver 3.01
中文描述: 高性能可配置8位微控制器版本3.01
文件頁(yè)數(shù): 2/7頁(yè)
文件大?。?/td> 101K
代理商: DR8051XP
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.
Scan test ready
1.3 GHz virtual
clock frequency in a 0.35u
technological process
P E R I P H E R AL S
DoCD debug unit
Processor execution control
Run
Halt
Step into instruction
Skip instruction
Read-write all processor contents
Program Counter (PC)
Program Memory
Internal (direct) Data Memory
Special Function Registers (SFRs)
External Data Memory
Hardware execution breakpoints
Program Memory
Internal (direct) Data Memory
Special Function Registers (SFRs)
External Data Memory
Hardware breakpoints activated at a certain
Program address (PC)
Address by any write into memory
Address by any read from memory
Address by write into memory a required data
Address by read from memory a required data
Three wire communication interface
Power Management Unit
Power management mode
Switchback feature
Stop mode
Interrupt Controller
2 priority levels
2 external interrupt sources
C O N F I G U R A T I O N
The following parameters of the DR8051CPU
core can be easy adjusted to requirements of
dedicated application and technology. Configu-
ration of the core can be prepared by effortless
changing appropriate constants in package file.
There is no need to change any parts of the
code.
- Harward
- von Neumann
- synchronous
- asynchronous
- used (0-7)
- unused
- used
- unused
- synchronous
- asynchronous
- 64 kB
- 16 MB
- used (0-7)
- unused
- subroutines
location
- used
- unused
- used
- unused
- used
- unused
Memory style
Program Memory type
Program Memory wait-
states
Program Memory writes
Internal Data Memory type
External Data Memory size
External Data Memory
wait-states
Interrupts
Power Management Mode
Stop mode
DoCD debug unit
D E L I V E R AB L E S
Source code:
VHDL Source Code or/and
VERILOG Source Code or/and
Encrypted, or plain text EDIF netlist
VHDL & VERILOG test bench environment
Active-HDL automatic simulation macros
ModelSim automatic simulation macros
Tests with reference responses
Technical documentation
Installation notes
HDL core specification
Datasheet
Synthesis scripts
Example application
Technical support
IP Core implementation support
3 months maintenance
相關(guān)PDF資料
PDF描述
DR8051 8-bit RISC Microcontroller ver 2.00
DR8051CPU High Performance Configurable 8-bit Microcontroller ver 3.01
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