參數(shù)資料
型號: DR8051XP
廠商: Electronic Theatre Controls, Inc.
元件分類: 8位微控制器
英文描述: High Performance Configurable 8-bit Microcontroller ver 3.01
中文描述: 高性能可配置8位微控制器版本3.01
文件頁數(shù): 1/7頁
文件大小: 101K
代理商: DR8051XP
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.
High Performance Configurable
8-bit Microcontroller
ver 3.01
O V E R V I E W
DR8051CPU is a
high performance, area
optimized
soft core of a single-chip 8-bit em-
bedded controller dedicated for operation with
fast
(typically on-chip) and
slow
(off-chip)
memories
. The core has been designed with a
special concern about
low power consump-
tion
. Additionally an advanced power man-
agement unit makes DR8051CPU core
perfect
for portable equipment
where low power
consumption is mandatory.
DR8051CPU soft core is 100% binary-
compatible with the industry standard 8051 8-
bit microcontroller. There are two configura-
tions of DR8051CPU:
Harward
where external
data and program buses are separated, and
von Neumann
with common program and ex-
ternal data bus. DR8051CPU has RISC archi-
tecture
6.7 times faster
compared to standard
architecture and executes
65-200 million in-
structions
per second. This performance can
also be exploited to great advantage in
low
power
applications where the core can be
clocked up to seven times more slowly than
the original implementation for no performance
penalty.
DR8051CPU is delivered with
fully auto-
mated testbench
and
complete set of tests
allowing easy package validation at each stage
of SoC design flow.
C P U F E AT U R E S
100% software compatible with industry
standard 8051
RISC architecture enables to execute in-
structions 6.7 times faster compared to
standard 8051
12 times faster multiplication
9.6 times faster division
Up to 256 bytes of internal (on-chip) Data
Memory
Up to 64K bytes of Program Memory
Up to 16M bytes of external (off-chip) Data
Memory
User programmable Program Memory Wait
States solution for wide range of memories
speed
User programmable External Data Memory
Wait States solution for wide range of
memories speed
De-multiplexed Address/Data bus to allow
easy connection to memory
Interface for additional Special Function
Registers
Fully synthesizable, static synchronous de-
sign with positive edge clocking and no in-
ternal tri-states
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