
ASAHI KASEI 
[AK4645] 
MS0543-E-00 
2006/09 
- 30 - 
 EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”) 
When PMPLL bit is “0”, the AK4645 becomes EXT mode. Master clock is input from MCKI pin, the internal PLL circuit 
is not operated. This mode is compatible with I/F of the normal audio CODEC. The clocks required to operate are MCKI 
(256fs, 512fs or 1024fs), LRCK (fs) and BICK (
≥
32fs). The master clock (MCKI) should be synchronized with LRCK. 
The phase between these clocks does not matter. The input frequency of MCKI is selected by FS1-0 bits (see Table 12). 
Mode 
FS3-2 bits 
FS1 bit 
FS0 bit 
MCKI Input 
Frequency 
256fs 
1024fs 
256fs 
512fs 
Sampling Frequency 
Range 
7.35kHz 
~
 48kHz 
7.35kHz 
~
 13kHz 
7.35kHz 
~
 48kHz 
7.35kHz 
~
 26kHz 
0 
1 
2 
3 
Don’t care 
Don’t care
Don’t care
Don’t care
Table 12. MCKI Frequency at EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
0 
0 
1 
1 
0 
1 
0 
1 
Default
The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. 
The out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the DAC output 
through LOUT/ROUT pins at fs=8kHz is shown in Table 13. 
MCKI 
S/N 
(fs=8kHz, 20kHzLPF + A-weighted)
83dB 
93dB 
93dB 
256fs 
512fs 
1024fs 
Table 13. Relationship between MCKI and S/N of LOUT/ROUT pins
The external clocks (MCKI, BICK and LRCK) should always be present whenever the ADC or DAC is in operation 
(PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4645 may draw 
excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If the external 
clocks are not present, the ADC and DAC should be in the power-down mode (PMADL=PMADR=PMDAC bits = “0”). 
AK4645 
DSP or 
μ
P
MCKI 
BICK 
LRCK 
SDTO 
SDTI 
BCLK 
LRCK 
SDTI 
SDTO 
MCKO 
1fs
≥
 32fs 
MCLK 
256fs, 512fs or 1024fs 
Figure 23. EXT Slave Mode