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參數(shù)資料
| 型號： | AK4645 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | Stereo CODEC with MIC/HP-AMP |
| 中文描述： | 立體聲編解碼器麥克風(fēng)/惠普腺苷 |
| 文件頁數(shù)： | 26/96頁 |
| 文件大?。?/td> | 821K |
| 代理商： | AK4645 |
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ASAHI KASEI
[AK4645]
MS0543-E-00
2006/09
- 26 -
When PLL reference clock input is LRCK or BICK pin, the sampling frequency is selected by FS3 and FS1-0 bits. (See
Table 7).
FS2 bit is “don’t care”.
Mode
FS3 bit
FS2 bit
FS1 bit
FS0 bit
0
0
Don’t care
0
1
0
Don’t care
0
2
0
Don’t care
1
3
0
Don’t care
1
6
1
Don’t care
1
7
1
Don’t care
1
Others
Others
Table 7. Setting of Sampling Frequency at PMPLL bit = “1” (Reference Clock = LRCK or BICK pin)
PLL Unlock State
1) PLL Master Mode (AIN3 bit = “0”; PMPLL bit = “1”, M/S bit = “1”)
In this mode, LRCK and BICK pins go to “L” and irregular frequency clock is output from MCKO pins at MCKO bit is
“1” before the PLL goes to lock state after PMPLL bit = “0”
“1”. If MCKO bit is “0”, MCKO pin goes to “L” (see
Table 8).
After the PLL is locked, a first period of LRCK and BICK may be invalid clock, but these clocks return to normal state
after a period of 1/fs.
When sampling frequency is changed, BICK and LRCK pins do not output irregular frequency clocks but go to “L” by
setting PMPLL bit to “0”.
MCKO pin
PLL State
MCKO bit = “0”
After that PMPLL bit “0”
“1”
“L” Output
PLL Unlock (except above case)
“L” Output
PLL Lock
“L” Output
Table 8. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
2) PLL Slave Mode (AIN3 bit = “0”, PMPLL bit = “1”, M/S bit = “0”)
In this mode, an invalid clock is output from MCKO pin before the PLL goes to lock state after PMPLL bit = “0”
“1”.
After that, the clock selected by Table 10 is output from MCKO pin when PLL is locked. ADC and DAC output invalid
data when the PLL is unlocked. For DAC, the output signal should be muted by writing “0” to DACL and DACH bits.
Sampling Frequency Range
7.35kHz
≤
fs
≤
8kHz
8kHz < fs
≤
12kHz
12kHz < fs
≤
16kHz
16kHz < fs
≤
24kHz
24kHz < fs
≤
32kHz
32kHz < fs
≤
48kHz
N/A
0
1
0
1
0
1
Default
MCKO bit = “1”
Invalid
Invalid
See Table 10
BICK pin
LRCK pin
“L” Output
Invalid
See Table 11
“L” Output
Invalid
1fs Output
MCKO pin
PLL State
MCKO bit = “0”
“L” Output
“L” Output
“L” Output
MCKO bit = “1”
Invalid
Invalid
Output
After that PMPLL bit “0”
“1”
PLL Unlock
PLL Lock
Table 9. Clock Operation at PLL Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK4646EZ | Stereo CODEC with MIC/SPK-AMP |
| AK4646 | Stereo CODEC with MIC/SPK-AMP |
| AK4646EN | Stereo CODEC with MIC/SPK-AMP |
| AK4647 | Stereo CODEC with MIC/HP-AMP |
| AK4647VN | Stereo CODEC with MIC/HP-AMP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4645EN | 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with MIC/HP-AMP |
| AK4645ENP-L | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述: |
| AK4645EZ | 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with MIC/HP-AMP |
| AK4646 | 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with built-in MIC/SPK amplifier |
| AK4646_11 | 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with MIC/SPK-AMP |
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