
ASAHI KASEI
[AK4645]
MS0543-E-00
2006/09
- 13 -
DC CHARACTERISTICS
(Ta=25
°
C; AVDD, DVDD=2.6
~
3.6V; TVDD=1.6
~
3.6V; HVDD=2.6
~
5.25V)
Parameter
High-Level Input Voltage
2.2V
≤
TVDD
≤
3.6V
1.6V
≤
TVDD<2.2V
Low-Level Input Voltage
2.2V
≤
TVDD
≤
3.6V
1.6V
≤
TVDD<2.2V
High-Level Output Voltage
(Iout=
200
μ
A)
Low-Level Output Voltage
(Except SDA pin: Iout=200
μ
A)
(SDA pin: Iout=3mA)
Input Leakage Current
SWITCHING CHARACTERISTICS
(Ta=25
°
C; AVDD, DVDD=2.6
~
3.6V; TVDD=1.6
~
3.6V; HVDD=2.6
~
5.25V; C
L
=20pF; unless otherwise specified)
Parameter
Symbol
PLL Master Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
MCKO Output Timing
Frequency
fMCK
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
256fs at fs=32kHz, 29.4kHz
dMCK
LRCK Output Timing
Frequency
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BICK Output Timing
Period
BCKO bit = “0”
tBCK
BCKO bit = “1”
tBCK
Duty Cycle
dBCK
PLL Slave Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
MCKO Output Timing
Frequency
fMCK
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
256fs at fs=32kHz, 29.4kHz
dMCK
LRCK Input Timing
Frequency
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BICK Input Timing
Period
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
Symbol
VIH
VIH
VIL
VIL
VOH
VOL
VOL
Iin
min
typ
-
-
-
-
-
-
-
-
max
-
-
Units
V
V
V
V
V
70
%
TVDD
75
%
TVDD
-
-
TVDD
0.2
-
-
-
30
%
TVDD
25
%
TVDD
-
0.2
0.4
±
10
V
V
μ
A
min
typ
max
Units
11.2896
0.4/fCLK
0.4/fCLK
-
-
-
27
-
-
MHz
ns
ns
0.2352
40
-
-
12.288
60
-
MHz
%
%
50
33
7.35
-
-
-
48
-
-
kHz
ns
%
tBCK
50
-
-
-
1/(32fs)
1/(64fs)
50
-
-
-
ns
ns
%
11.2896
0.4/fCLK
0.4/fCLK
-
-
-
27
-
-
MHz
ns
ns
0.2352
40
-
-
12.288
60
-
MHz
%
%
50
33
7.35
-
-
-
48
kHz
ns
%
tBCK
60
45
1/fs
tBCK
55
1/(64fs)
0.4 x tBCK
0.4 x tBCK
-
-
-
1/(32fs)
-
-
ns
ns
ns