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參數(shù)資料
| 型號(hào)： | DP8441 |
| 文件頁數(shù)： | 10/46頁 |
| 文件大小： | 644K |
| 代理商： | DP8441 |
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4.0 Programming and Resetting
4.1 RESET
After power up, the DP8440/41 must be reset and pro-
grammed before it can be used to access the DRAM. Reset
is accomplished by asserting the input RESET for at least
16 positive edges of CLK after V
CC
stabilizes. After reset,
the part can be programmed.
4.2 PROGRAMMING
Programming is accomplished by presenting a valid pro-
gramming selection on the row, column, bank selects and
ECAS inputs and toggling the ML input from low to high.
When ML goes high the part is programmed. After the first
programming after a reset the part will enter a 60 ms initiali-
zation period. During this period the controller will refresh
the memory, so further DRAM warm up cycles are not nec-
essary. The user can program the part on the fly by pulsing
ML low and high (provided that no refresh is in progress)
while a valid programming selection is on the address bus.
The part will not enter the initialization period when it is only
re-programmed.
TL/F/11718–4
FIGURE 5. Reset
TL/F/11718–5
FIGURE 6. Programming
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