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參數(shù)資料
| 型號： | DP83848C-POE-EK |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 5/86頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION DP83848C |
| 標準包裝： | 1 |
| 系列： | PowerWise® |
| 主要目的： | 特殊用途 DC/DC，以太網(wǎng)供電（POE） |
| 輸出及類型： | 1，隔離 |
| 功率 - 輸出： | 24W |
| 輸出電壓： | 3.3V |
| 電流 - 輸出： | 7.3A |
| 輸入電壓： | 39 ~ 57V |
| 穩(wěn)壓器拓撲結構： | 回掃 |
| 頻率 - 開關： | 250kHz |
| 板類型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | LM5072 |
| 相關產(chǎn)品： | DP83848CVVX/NOPBTR-ND - TXRX ETHERNET PHYTER 48-LQFP DP83848CVV-ND - IC TXRX ETHERNET PHYTER 48-LQFP |
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12
DP
83
84
8C
1.5 Reset and Power Down
1.6 Strap Options
The DP83848C uses many of the functional pins as strap options. The values of these pins are sampled during reset and
used to strap the device into specific modes of operation. The strap option pin assignments are defined below. The func-
tional pin name is indicated in parentheses.
A 2.2 k
resistor should be used for pull-down or pull-up to change the default strap option. If the default option is
required, then there is no need for external pull-up or pull down resistors. Since these pins may have alternate functions
after reset is deasserted, they should not be connected directly to VCC or GND.
Signal Name
Type
Pin #
Description
RESET_N
I, PU
29
RESET: Active Low input that initializes or re-initializes the
DP83848C. Asserting this pin low for at least 1
s will force a reset
process to occur. All internal registers will re-initialize to their de-
fault states as specified for each bit in the Register Block section.
All strap options are re-initialized as well.
PWR_DOWN/INT
I, OD, PU
7
See Section 5.5 for detailed description.
The default function of this pin is POWER DOWN.
POWER DOWN: The pin is an active low input in this mode and
should be asserted low to put the device in a Power Down mode.
INTERRUPT: The pin is an open drain output in this mode and will
be asserted low when an interrupt condition occurs. Although the
pin has a weak internal pull-up, some applications may require an
external pull-up resister. Register access is required for the pin to
be used as an interrupt mechanism. See Section 5.5.2 Interrupt
Mechanism for more details on the interrupt mechanisms.
Signal Name
Type
Pin #
Description
PHYAD0 (COL)
PHYAD1 (RXD_0)
PHYAD2 (RXD_1)
PHYAD3 (RXD_2)
PHYAD4 (RXD_3)
S, O, PU
S, O, PD
42
43
44
45
46
PHY ADDRESS [4:0]: The DP83848C provides five PHY ad-
dress pins, the state of which are latched into the PHYCTRL reg-
ister at system Hardware-Reset.
The DP83848C supports PHY Address strapping values 0
(<00000>) through 31 (<11111>). A PHY Address of 0 puts the
part into the MII Isolate Mode. The MII isolate mode must be se-
lected by strapping Phy Address 0; changing to Address 0 by reg-
ister write will not put the Phy in the MII isolate mode. Please refer
to section 2.3 for additional information.
PHYAD0 pin has weak internal pull-up resistor.
PHYAD[4:1] pins have weak internal pull-down resistors.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DP83848CVV | 制造商:Texas Instruments 功能描述:IC, 10/100 ETHERNET PHY, SMD, LQFP48 |
| DP83848CVV/NOPB | 功能描述:以太網(wǎng) IC PHYTER COMMERCIAL TEMP SGL PORT RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| DP83848CVV/NOPB | 制造商:Texas Instruments 功能描述:Ethernet Transceiver |
| DP83848CVVX | 制造商:Texas Instruments 功能描述:PHY 1-CH 10Mbps/100Mbps 48-Pin LQFP T/R |
| DP83848CVVX/NOPB | 功能描述:以太網(wǎng) IC PHYTER COMMERCIAL TEMP SGL PORT RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
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