參數(shù)資料
型號(hào): DP83848C-MAU-EK
廠商: National Semiconductor
文件頁(yè)數(shù): 76/86頁(yè)
文件大?。?/td> 0K
描述: BOARD EVALUATION DP83848C
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,以太網(wǎng)
已用 IC / 零件: DP83848C
已供物品:
相關(guān)產(chǎn)品: DP83848CVVX/NOPBTR-ND - TXRX ETHERNET PHYTER 48-LQFP
DP83848CVV-ND - IC TXRX ETHERNET PHYTER 48-LQFP
77
www.national.com
DP
83
84
8
C
8.2.23 100BASE-TX Signal Detect Timing
Note: The signal amplitude on PMD Input Pair must be TP-PMD compliant.
8.2.24 100 Mb/s Internal Loopback Timing
Note1: Due to the nature of the descrambler function, all 100BASE-TX Loopback modes will cause an initial “dead-time”
of up to 550
s during which time no data will be present at the receive MII outputs. The 100BASE-TX timing specified is
based on device delays after the initial 550
s “dead-time”.
Note2: Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN.
Parameter
Description
Notes
Min
Typ
Max
Units
T2.23.1
SD Internal Turn-on Time
1
ms
T2.23.2
SD Internal Turn-off Time
350
s
Parameter
Description
Notes
Min
Typ
Max
Units
T2.24.1
TX_EN to RX_DV Loopback
100 Mb/s internal loopback mode
240
ns
SD+ internal
PMD Input Pair
TX_CLK
TX_EN
TXD[3:0]
CRS
RX_CLK
RXD[3:0]
RX_DV
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參數(shù)描述
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