參數(shù)資料
型號: DP83848C-MAU-EK
廠商: National Semiconductor
文件頁數(shù): 63/86頁
文件大?。?/td> 0K
描述: BOARD EVALUATION DP83848C
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,以太網(wǎng)
已用 IC / 零件: DP83848C
已供物品:
相關(guān)產(chǎn)品: DP83848CVVX/NOPBTR-ND - TXRX ETHERNET PHYTER 48-LQFP
DP83848CVV-ND - IC TXRX ETHERNET PHYTER 48-LQFP
65
www.national.com
DP
83
84
8
C
8.2.2 Reset Timing
Note: It is important to choose pull-up and/or pull-down resistors for each of the hardware configuration pins that provide
fast RC time constants in order to latch-in the proper value prior to the pin transitioning to an output driver.
Parameter
Description
Notes
Min
Typ
Max
Units
T2.2.1
Post RESET Stabilization time
prior to MDC preamble for reg-
ister accesses
MDIO is pulled high for 32-bit serial man-
agement initialization
3
s
T2.2.2
Hardware Configuration Latch-
in Time from the Deassertion
of RESET (either soft or hard)
Hardware Configuration Pins are de-
scribed in the Pin Description section
3
s
T2.2.3
Hardware Configuration pins
transition to output drivers
50
ns
T2.2.4
RESET pulse width
X1 Clock must be stable for at min. of 1us
during RESET pulse low time.
1
s
Vcc
Hardware
RESET_N
MDC
32 clocks
Latch-In of Hardware
Configuration Pins
Dual Function Pins
Become Enabled As Outputs
input
output
X1 clock
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參數(shù)描述
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DP83848CVV 制造商:Texas Instruments 功能描述:IC, 10/100 ETHERNET PHY, SMD, LQFP48
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DP83848CVV/NOPB 制造商:Texas Instruments 功能描述:Ethernet Transceiver
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