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參數(shù)資料
| 型號： | DP3S1MX32PY5-10CI |
| 英文描述： | x32 SRAM Module |
| 中文描述： | X32號的SRAM模塊 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 510K |
| 代理商： | DP3S1MX32PY5-10CI |
32 Mega bit CMOS SRAM
DP3S1MX32PY5
AD VANCED IN FOR MA TION
DE SCRIP TION:
The DP3S1MX32PY5 is a 1M x 32 SRAM module
that utilizes the new and innovative space saving
TSOP stacking technology. The module is
constructed of two 1M x 16 SRAM’s that are
configured as a 1M x 32.
The DP3S1MX32PY5 module features high speed
access times with common data inputs and outputs.
FEA TURES:
Organizations Available: 1M x 32
Access Times:
3.3
±
0.3** Volt Power Requirement
Fully Static Operation - No clock or refresh
required
TTL-compatible Inputs and Outputs
80-Pin Surface Mount LP-Stack
10*, 12, 15, 20ns
* 0°-70° only.
** 5% for 10ns only.
1
30A244-00
REV. A
PIN-OUT DI A GRAM
FUNC TIONAL BLOCK DI A GRAM
PIN NAMES
Address Inputs
Data Input/Output
Stack Enable
Write Enable
Output Enable
Byte Select I/O0 - I/O7
Byte Select I/O8 - I/O15
Byte Select I/O16 - I/O23
Byte Select I/O24 - I/O31
Power (+ 3.3V)
Ground
Not Usable
A0 - A19
I/O0 - I/O31
CS
WE
OE
BS0
BS1
BS2
BS3
V
DD
V
SS
NU.
2Mx8/1Mx16/512Kx32, 12 - 20ns, Surface Mount
30A244-00
A
This document contains information on a product under consideration for
development at Dense-Pac Microsystems, Inc. Dense-Pac reserves the right to
change or discontinue information on this product without prior notice.
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