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參數(shù)資料
| 型號(hào)： | DM9801E |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 1M home Phonrline Network Physical Layer Single Chip Transceiver |
| 中文描述： | 100萬家庭Phonrline網(wǎng)絡(luò)物理層單芯片收發(fā)器 |
| 文件頁數(shù)： | 5/61頁 |
| 文件大?。?/td> | 589K |
| 代理商： | DM9801E |
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DM9801
1M Home Phoneline Network Physical Layer Single Chip Transceiver
Preliminary
Version: DM9801-DS-P02
March 20, 2000
5
Pin Description
(Continued)
Pin No.
Pin Name
Station Interface: Receive Data, Transmit Data and Management (Continued)
67
MDIO
Or
SCS#
station management entity or the PHY. This pin requires a 1.5K
pull-up
resistor.
Serial Interface Chip Select (GPSI Mode, INTFSEL = 1):
SCS# is a bi-directional management chip select signal that may be driven
by the station management entity or the PHY.
(Active low)
97
Or
SRXDAT
Receive data output pin for serial data to the GPSI.
96
Receive data output pin, bit 1, for nibble data to the
95
Receive data output pin, bit 2, for nibble data to the MII
94
Receive data output pin, bit 3, for nibble data to the MII
90
RX_CLK
Or
SRDCLK
reference clock, to clock out nibble data from the MII when in MII interface
mode.
Serial Receive Data Clock (GPSI Mode, INTFSEL = 1):
SRDCLK is an output from the DM9801. Used as the receive reference
clock to clock out the SRXDATA when in GPSI interface mode.
91
RX_DV
Or
SO
Serial Data Output (GPSI Mode, INTFSEL = 1):
This is the serial data output pin from the DM9801 for the SPI bus. The SPI
bus operation is only valid if GPSI mode is selected.
93
CRS
O,Z
Carrier Sense:
This pin is asserted high to indicate the presence of carrier due to receive
or transmit activities.
92
COL
or
CLSN
Collision Detect (GPSI Mode, INTFSEL = 1):
CLSN is asserted high to indicate detection of collision condition.
I/O
Description
I/O,Z
MII Serial Management Data (MII Mode, INTFSEL = 0):
Bi-directional management instruction/data signal that may be driven by the
RXD0
O,Z
Receive Data Bit 0 (MII Mode, INTFSEL = 0):
Receive data output pin, bit 0, for nibble data to the MII
Serial Receive Data Bit (GPSI Mode, INTFSEL = 1):
RXD1
O,Z
Receive Data Bit 1:
RXD2
O,Z
Receive Data Bit 2:
RXD3
O,Z
Receive Data Bit 3:
O,Z
MII Receive Clock (MII Mode, INTFSEL = 0):
RX_CLK is an output pin from the DM9801. Used as the receive data
O,Z
Receive Data Valid (MII Mode, INTFSEL = 0):
RX_DV is asserted high to indicate that valid data is present on RXD[3:0].
O,Z
Collision Detect MII Mode, INTFSEL = 0):
COL is asserted high to indicate detection of collision condition.
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