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參數(shù)資料
| 型號： | DM9801E |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 1M home Phonrline Network Physical Layer Single Chip Transceiver |
| 中文描述： | 100萬家庭Phonrline網(wǎng)絡(luò)物理層單芯片收發(fā)器 |
| 文件頁數(shù)： | 11/61頁 |
| 文件大?。?/td> | 589K |
| 代理商： | DM9801E |
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DM9801
1M Home Phoneline Network Physical Layer Single Chip Transceiver
MII Interface
(continued)
Preliminary
Version: DM9801-DS-P02
March 20, 2000
11
RXD (receive data) is a nibble (4 bits) of data that are
sampled by the reconciliation sublayer synchronously with
respect to RX_CLK. For each RX_CLK period that
RX_DV is asserted, RXD (3:0) are transferred from the
PHY to the MAC reconciliation sublayer.
RX_CLK (receive clock) output to the MAC reconciliation
sublayer is a clock that provides the timing reference for
the transfer of the RX_DV, RXD, and RX_ER signals.
RX_DV (receive data valid) input from the PHY to indicate
the PHY is presenting recovered and decoded nibbles to
the MAC reconciliation sublayer. To interpret a receive
frame correctly by the reconciliation sublayer, RX_DV
must encompass the frame starting no later than the Start-
of-Frame delimiter and excluding any End-Stream
delimiter.
CRS (carrier sense) is asserted by the PHY when either
the transmit or receive medium is non-idle and deasserted
by the PHY when the transmit and receive medium are
idle.
MII Serial Management
The MII serial management interface consists of a
data interface, basic register set, and a serial
management interface to the register set. Through
this interface it is possible to control and configure
multiple PHY devices, get status and error
information, and determine the type and capabilities
of the attached PHY device(s).
MII Interface Transmit and Receive Timing Diagram
TX_CLK
The DM9801 management functions correspond to
MII specification for IEEE 802.3u-1995 (Clause 22)
for registers 0 through 6 with vendor-specific
registers 16 through 31.
In read/write operation, the management data frame
is 64-bits long and starts with 32 contiguous logic
one bits (preamble) synchronization clock cycles on
MDC. The Start of Frame Delimiter (SFD) is
indicated by a <01> pattern followed by the
operation code (OP):<10> indicates Read operation
and <01> indicates Write operation. For read
operation, a 2-bit turnaround (TA) filing between
Register Address field and Data field is provided for
MDIO to avoid contention. Following the turnaround
time, 16-bit data is read from or written to the
management registers.
Serial Management Interface
The serial control interface uses a simple two-wired
serial interface to obtain and control the status of
the physical layer through the MII interface. The
serial control interface consists of MDC
(Management Data Clock), and MDI/O
(Management Data Input/Output) signals.
The MDIO pin is bi-directional and may be shared
by up to 32 devices.
RX_CLK
TX_EN
TXD
CRS
RXD
COL
RX_DV
0
0
RX_CLK and TX_CLK are synchronized. All signals are inactive. The period of the two clock is 2333.3 ns.
Idle State
Figure 2
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