參數(shù)資料
型號(hào)： DM9331A
文件頁(yè)數(shù)： 25/43頁(yè)
文件大小： 509K
代理商： DM9331A
DM9331
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
Preliminary 25
Version: DM9331-DS-P02
September 21, 2001
DAVICOM Specified Interrupt Register – 21
Bit
21.15
Bit Name
INTR PEND
Default
0, RO
Description
Interrupt pending :
Indicates that the interrupt is pending and is cleared by the current
read. This bit shows the same result as bit 0. (INTR Status)
Reserved
21.14-
21.12
21.11
Reserved
0, RO
FDX mask
1, RW
Full-duplex interrupt mask :
When this bit is set, the Duplex status change will not generate the
interrupt
Reserved
Link interrupt mask :
When this bit is set, the link status change will not generate the
interrupt
Master interrupt mask :
When this bit is set, no interrupts will be generated under any
condition.
Reserved
Duplex status change interrupt :
“1” indicates a change of duplex since last register read. A read of
this register will clear this bit.
Reserved
Link status change interrupt :
“1” indicates a change of link since last register read. A read of this
register will clear this bit.
Reserved
21.10
21.9
Reserved
LINK mask
1, RW
1, RW
21.8
INTR mask
1, RW
21.7-21.5
21.4
Reserved
FDX change
0, RO
0,RO/LH
21.3
21.2
Reserved
LINK change
0, RO/LH
0, RO/LH
21.1
Reserved
0, RO
21.0
INTR status
0, RO/LH
Interrupt status :
The status of MDINTR#. “1” indicates that the interrupt mask is off
that one or more of the change bits are set. A read of this register
will clear this bit.
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