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參數(shù)資料
| 型號(hào)： | DM9331A |
| 文件頁(yè)數(shù)： | 11/43頁(yè) |
| 文件大?。?/td> | 509K |
| 代理商： | DM9331A |
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DM9331
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
Preliminary 11
Version: DM9331-DS-P02
September 21, 2001
100Base-TX Operation
The 100Base-TX transmitter receives 2-bits data clocked in
at 50MHz from the MCI, and outputs a scrambled 5-bit
encoded MLT-3 signal to the media at 100Mbps. The on-
chip clock circuit converts the 25MHz clock into a 125MHz
clock for internal use.
These two busses include various controls and signal
indications that facilitate data transfers between the DM9331
chip set.
100Base-TX Transmit
The 100Base-TX transmitter consists of the functional
blocks shown in figure 2. The 100Base-TX transmit section
converts 2-bits synchronous data provided by the MCI to a
scrambled MLT-3 125 million symbols per second serial
data stream.
MCI
Signals
MCI
Interface/
Control
4B/5B
Encoder
4B/5B
Decoder
Register
Code-
group
Alignment
Descrambler
Serial to
Parallel
NRZI
to
NRZ
RX
CRM
MLT-3 to
NRZI
Adaptive
EQ
Digital
Logic
Scrambler
Parallel
to Serial
NRZ
to
NRZI
NRZI to
MLT-3
MLT-3
Driver
Rise/Fall
Time
CTL
TX CGM
LED
Driver
Auto-Negotiation
TX/RX Module
125M CLK
25M CLK
LED1-3#
50M OSCI
TX±
RX±
TX±
RX±
Figure 2
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相關(guān)代理商/技術(shù)參數(shù) |
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| DM9331AE | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip |
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| DM9334 WAF | 制造商:Texas Instruments 功能描述: |
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