參數(shù)資料
型號(hào): DM9161
廠商: Electronic Theatre Controls, Inc.
英文描述: 10/100 Mbps FAST ETHERNET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER
中文描述: 10/100 Mbps快速以太網(wǎng)物理層單芯片收發(fā)器
文件頁數(shù): 37/47頁
文件大?。?/td> 561K
代理商: DM9161
DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
Final 37
Version: DM9161-DS-F02
May 10,2002
9.4.12 MII 10BASE-T Receive Nibble Timing Parameters
Symbol
t
RXs
t
RXh
t
RXpd
t
1
t
2
t
3
t
4
Parameter
Min.
5
5
---
1
---
1
1
Typ.
---
---
7
14
---
2
10
Max.
---
---
---
20
3
4
15
Unit
ns
ns
BT
BT
BT
BT
BT
Conditions
RXD [0:3), RXDV, RXER Setup To RXCLK High
RXD [0:3], RXDV, RXER Hold From RXCLK High
RXI In To RXD [0:3] Out (Rx Latency)
CRS Asserted To RXD [0:3], RXDV, RXER
CRS De-asserted To RXD [0:3], RXDV, RXER
RXI In To CRS Asserted
RXI Quiet To CRS De-asserted
9.4.13 MII 10BASE-T Receive Nibble Timing Diagram
RXCLK
t
2
t
1
t
TX
pd
RXD [0:3],
RXDV, RXER
CRS
RX+/-
t
RX
S
t
RX
h
t
4
t
3
9.4.14 Auto-negotiation and Fast Link Pulse Timing Parameters
Symbol
t
1
t
2
t
3
t
4
t
5
-
Parameter
Min.
---
55.5
111
-
8
17
Typ.
100
62.5
125
2
Max.
---
69.5
139
-
24
33
Unit
ns
us
us
ms
ms
pulse
Conditions
Clock/Data Pulse Width
Clock Pulse To Data Pulse Period
Clock Pulse To Clock Pulse Period
FLP Burst Width
FLP Burst To FLP Burst Period
Clock/Data Pulses in a Burst
DATA = 1
9.4.15 Auto-negotiation and Fast Link Pulse Timing Diagram
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