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參數資料
| 型號： | DM9161 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 10/100 Mbps FAST ETHERNET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER |
| 中文描述： | 10/100 Mbps快速以太網物理層單芯片收發(fā)器 |
| 文件頁數： | 22/47頁 |
| 文件大?。?/td> | 561K |
| 代理商： | DM9161 |
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DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
22
Final
Version: DM9161-DS-F02
May 10,2002
8.1 Basic Mode Control Register (BMCR) -
00
Bit
0.15
Bit Name
Reset
Default
0, RW/SC
Description
Reset
1=Software reset
0=Normal operation
This bit sets the status and controls the PHY registers to their default
states. This bit, which is self-clearing, will keep returning a value of
one until the reset process is completed
Loopback
Loop-back control register
1 = Loop-back enabled
0 = Normal operation
When in 100Mbps operation mode, setting this bit may cause the
descrambler to lose synchronization and produce a 720ms "dead
time" before any valid data appears at the MII receive outputs
Speed Select
1 = 100Mbps
0 = 10Mbps
Link speed may be selected either by this bit or by auto-negotiation.
When auto-negotiation is enabled and bit 12 is set, this bit will return
auto-negotiation selected medium type
Auto-negotiation Enable
1 = Auto-negotiation is enabled, bit 8 and 13 will be in auto-negotiation
status
Power Down
While in the power-down state, the PHY should respond to
management transactions. During the transition to power-down state
and while in the power-down state, the PHY should not generate
spurious signals on the MII
1=Power down
0=Normal operation
Isolate
1 = Isolates the DM9161 from the MII with the exception of the serial
management. (When this bit is asserted, the DM9161 does not
respond to the TXD [0:3], TX_EN, and TX_ER inputs, and it shall
present a high impedance on its TX_CLK, RX_CLK, RX_DV, RX_ER,
RX [0:3], COL and CRS outputs. When PHY is isolated from the MII it
shall respond to the management transactions)
0 = Normal operation
Restart Auto-negotiation
1 = Restart auto-negotiation. Re-initiates the auto-negotiation
process. When auto-negotiation is disabled (bit 12 of this register
cleared), this bit has no function and it should be cleared. This bit is
self-clearing and it will keep returning to a value of 1 until auto-
negotiation is initiated by the DM9161. The operation of the auto-
negotiation process will not be affected by the management entity that
clears this bit
0 = Normal operation
0.14
Loopback
0, RW
0.13
Speed selection
1, RW
0.12
Auto-negotiation
enable
1, RW
0.11
Power down
0, RW
0.10
Isolate
0,RW
0.9
Restart
Auto-negotiation
0,RW/SC
相關PDF資料 |
PDF描述 |
|---|---|
| DM9161E | 10/100 Mbps FAST ETHERNET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER |
| DM9301 | 100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter |
| DM9301F | 100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter |
| DM9324 | 5-Bit Comparator |
| DM9324N | 5-Bit Comparator |
相關代理商/技術參數 |
參數描述 |
|---|---|
| DM9161_08 | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps Fast Ethernet Physical Layer TX/FX Single Chip Transceiver |
| DM9161A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10/100 MBPS FAST ETHEMET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER |
| DM9161A_09 | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver |
| DM9161AE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10/100 MBPS FAST ETHEMET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER |
| DM9161AEP | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver |
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