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參數(shù)資料
| 型號： | DM9161 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 10/100 Mbps FAST ETHERNET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER |
| 中文描述： | 10/100 Mbps快速以太網(wǎng)物理層單芯片收發(fā)器 |
| 文件頁數(shù)： | 30/47頁 |
| 文件大?。?/td> | 561K |
| 代理商： | DM9161 |
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DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
30
Final
Version: DM9161-DS-F02
May 10,2002
8.10 10BASE-T Configuration/Status (10BTCSR) - 18
Bit
18.15
Bit Name
Reserved
Default
0, RO
Description
Reserved
Read as 0, ignore on write
Link Pulse Enable
1 = Transmission of link pulses enabled
0 = Link pulses disabled, good link condition forced
This bit is valid only in 10Mbps operation
Heartbeat Enable
1 = Heartbeat function enabled
0 = Heartbeat function disabled
When the DM9161 is configured for full duplex operation, this bit will
be ignored (the collision/heartbeat function is invalid in full duplex
mode)
Squelch Enable
1 = Normal squelch
0 = Low squelch
Jabber Enable
Enables or disables the Jabber function when the DM9161 is in
10BASE-T full duplex or 10BASE-T transceiver loopback mode
1 = Jabber function enabled
0 = Jabber function disabled
10BASE-T GPSI Mode
1 = 10BASE-T GPSI mode selected
0 = 10BASE-T MII mode selected
GPSI mode is not supported for 100Mbps operation
Reserved
Read as 0, ignore on write
Polarity Reversed
When this bit is set to 1, it indicates that the 10Mbps cable polarity is
reversed. This bit is automatically set and cleared by 10BASE-T
module
18.14
LP_EN
1, RW
18.13
HBE
1,RW
18.12
SQUELCH
1, RW
18.11
JABEN
1, RW
18.10
10BT_SER
0,RW
18.9-18.1
Reserved
0, RO
18.0
POLR
0, RO
8.11 DAVICOM Specified Interrupt Register
–
21
Bit
21.15
Bit Name
INTR PEND
Default
0, RO
Description
Interrupt Pending
Indicates that the interrupt is pending and is cleared by the current
read. This bit shows the same result as bit 0. (INTR Status)
Reserved
21.14-
21.12
21.11
Reserved
0, RO
FDX mask
1, RW
Full-duplex Interrupt Mask
When this bit is set, the Duplex status change will not generate the
interrupt
Speed Interrupt Mask
When this bit is set, the Speed status change will not generate the
interrupt
Link Interrupt Mask
21.10
SPD mask
1, RW
21.9
LINK mask
1, RW
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DM9161E | 10/100 Mbps FAST ETHERNET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER |
| DM9301 | 100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter |
| DM9301F | 100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter |
| DM9324 | 5-Bit Comparator |
| DM9324N | 5-Bit Comparator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DM9161_08 | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps Fast Ethernet Physical Layer TX/FX Single Chip Transceiver |
| DM9161A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10/100 MBPS FAST ETHEMET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER |
| DM9161A_09 | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver |
| DM9161AE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10/100 MBPS FAST ETHEMET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER |
| DM9161AEP | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver |
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