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參數(shù)資料
| 型號： | DM9102AF |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Single Chip Fast Ethernet NIC controller |
| 中文描述： | 單芯片快速以太網(wǎng)網(wǎng)卡控制器 |
| 文件頁數(shù)： | 18/77頁 |
| 文件大小： | 459K |
| 代理商： | DM9102AF |
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DM9102A
Single Chip Fast Ethernet NIC controller
18
Final
Version: DM9102A-DS-F03
August 28, 2000
Miscellaneous Function (xxxxxx0c - PCILT)
31
16
15
0
8
7
23
24
BIST
Header Type
Latency Timer
Cache Line Size
Built-In Self Test
Header Type
Latency Timer For The Bus Master
Cache Line Size For Memory Read
Bit
31:24
23:16
15:8
Default
00h
00h
00h
Type
RO
RO
RW
Description
Built In Self Test ( 00h Means Not Implementation)
Header Type ( 00h Means single function with Predefined Header Type )
Latency Timer For The Bus Master.
The latency timer is guaranteed by the system and measured by clock cycles.
When the FRAME# asserted at the beginning of a master period by the DM9102A,
the value will be copied into a counter and start counting down. If the FRAME# is
de-asserted prior to count expiration, this value is meaningless. When the count
expires before GNT# is de-asserted, the master transaction will be terminated as
soon as the GNT# is removed.
While GNT# signal is removed and the counter is non-zero, the DM9102A will
continue with its data transfers until the count expires. The system host will read
MIN_GNT and MAX_LAT registers to determine the latency requirement for the
device and then initialize the latency timer with an appropriate value.
The reset value of Latency Timer is determined by BIOS.
Cache line Size For Memory Read Mode Selection ( 00h Means Not
Implementation For Use)
7:0
00h
RO
I/O Base Address (xxxxxx10 - PCIIO)
31
0
1
7
8
1
0000000
I/O Base Address
I/O Base Address
PCI I/O Range
I/O or Memory Space Indicator
相關PDF資料 |
PDF描述 |
|---|---|
| DM9102AT | Single Chip Fast Ethernet NIC controller |
| DM9108APPLICATIONENGINEERINGNOTESONE | DM9108 Application Engineering notes one |
| DM9108APPLICATIONENGINEERINGNOTESTHREE | DM9108 Application Engineering notes three |
| DM9108APPLICATIONENGINEERINGNOTESTWO | DM9108 Application Engineering notes two |
| DM9161A | 10/100 MBPS FAST ETHEMET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DM9102AT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single Chip Fast Ethernet NIC controller |
| DM9102D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE CHIP FAST ETHEMET NIC CONTROLLER |
| DM9102DE | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Single Chip Fast Ethernet NIC Controller |
| DM9102DEP | 制造商:DAVICOM 功能描述:IC ENET CNTRL 10/100M PHY 1 制造商:DAVICOM 功能描述:IC ENET CNTRL 10/100M PHY 128LQFP 制造商:DAVICOM 功能描述:IC, ENET CNTRL, 10/100M PHY, 128LQFP 制造商:DAVICOM 功能描述:IC, ENET CNTRL, 10/100M PHY, 128LQFP; Data Rate:100Mbps; Ethernet Type:IEEE 802.3u; Supply Voltage Min:2.375V; Supply Voltage Max:2.625V; Digital IC Case Style:LQFP; No. of Pins:128; Interface Type:PCI; Operating Temperature Min:0C;;RoHS Compliant: Yes |
| DM9102H | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Single Chip Fast Ethernet NIC Controller |
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