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參數(shù)資料
| 型號： | DM74KS112AM |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs |
| 中文描述： | LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16 |
| 封裝： | 0.150 INCH, MS-012, SOIC-16 |
| 文件頁數(shù)： | 3/5頁 |
| 文件大?。?/td> | 52K |
| 代理商： | DM74KS112AM |
3
www.fairchildsemi.com
D
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Note 6:
All typicals are at V
CC
=
5V, T
A
=
25
°
C.
Note 7:
Not more than one output should be shorted at a time, and the duration should not exceed one second. For devices, with feedback from the outputs,
where shorting the outputs to ground may cause the outputs to change logic state an equivalent test may be performed where V
O
=
2.125V with the minimum
and maximum limits reduced by one half from their stated values. This is very useful when using automatic test equipment.
Note 8:
With all outputs OPEN, I
CC
is measured with the Q and Q outputs HIGH in turn. At the time of measurement the clock is grounded.
Switching Characteristics
at V
CC
=
5V and T
A
=
25
°
C
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 6)
V
I
V
OH
Input Clamp Voltage
HIGH Level
Output Voltage
V
CC
=
Min, I
I
=
18 mA
V
CC
=
Min, I
OH
=
Max
V
IL
=
Max, V
IH
=
Min
V
CC
=
Min, I
OL
=
Max
V
IL
=
Max, V
IH
=
Min
I
OL
=
4 mA, V
CC
=
Min
V
CC
=
Max, V
I
=
7V
1.5
V
2.7
3.4
V
V
OL
LOW Level
Output Voltage
0.35
0.5
V
0.25
0.4
I
I
Input Current @ Max
Input Voltage
J, K
Clear
Preset
0.1
0.3
0.3
mA
Clock
J, K
Clear
0.4
20
60
I
IH
HIGH Level Input Current
V
CC
=
Max, V
I
=
2.7V
μ
A
Preset
Clock
J, K
60
80
0.4
0.8
0.8
0.8
100
6
I
IL
LOW Level Input Current
V
CC
=
Max, V
I
=
0.4V
Clear
Preset
Clock
mA
I
OS
I
CC
Short Circuit Output Current
Supply Current
V
CC
=
Max (Note 7)
V
CC
=
Max (Note 8)
20
mA
mA
4
From (Input)
R
L
=
2 k
Symbol
Parameter
To (Output)
C
L
=
15 pF
Min
30
C
L
=
50 pF
Min
25
Units
Max
Max
f
MAX
t
PLH
Maximum Clock Frequency
Propagation Delay Time
LOW-to-HIGH Level Output
MHz
Preset to Q
20
24
ns
t
PHL
Propagation Delay Time
HIGH-to-LOW Level Output
Preset to Q
20
28
ns
t
PLH
Propagation Delay Time
LOW-to-HIGH Level Output
Clear to Q
20
24
ns
t
PHL
Propagation Delay Time
HIGH-to-LOW Level Output
Clear to Q
20
28
ns
t
PLH
Propagation Delay Time
LOW-to-HIGH Level Output
Clock to Q or Q
20
24
ns
t
PHL
Propagation Delay Time
HIGH-to-LOW Level Output
Clock to Q or Q
20
28
ns
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