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參數(shù)資料
| 型號： | DM74KS112AM |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs |
| 中文描述： | LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16 |
| 封裝： | 0.150 INCH, MS-012, SOIC-16 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大?。?/td> | 52K |
| 代理商： | DM74KS112AM |
2000 Fairchild Semiconductor Corporation
DS006382
www.fairchildsemi.com
August 1986
Revised March 2000
D
O
DM74LS112A
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop
with Preset, Clear, and Complementary Outputs
General Description
This device contains two independent negative-edge-trig-
gered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flop on the falling edge of
the clock pulse. The clock triggering occurs at a voltage
level and is not directly related to the transition time of the
falling edge of the clock pulse. Data on the J and K inputs
may be changed while the clock is HIGH or LOW without
affecting the outputs as long as the setup and hold times
are not violated. A low logic level on the preset or clear
inputs will set or reset the outputs regardless of the logic
levels of the other inputs.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
H
=
HIGH Logic Level
L
=
LOW Logic Level
X
=
Either LOW or HIGH Logic Level
↓
=
Negative Going Edge of Pulse
Q
0
=
The output logic level before the indicated input conditions were
established.
Toggle
=
Each output changes to the complement of its previous level on
each falling edge of the clock pulse.
Note 1:
This configuration is nonstable; that is, it will not persist when
preset and/or clear inputs return to their inactive (HIGH) level.
Order Number
DM74KS112AM
DM74LS112AN
Package Number
M16A
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs
Outputs
PR
L
H
L
H
H
H
H
CLR CLK
H
L
L
H
H
H
H
J
X
X
X
L
H
L
H
K
X
X
X
L
L
H
H
Q
H
L
Q
L
H
X
X
X
↓
↓
↓
↓
H
H (Note 1)
Q
0
H
L
H (Note 1)
Q
0
L
H
Toggle
H
H
X
X
Q
0
Q
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DM74LS112A | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs(雙負(fù)邊緣觸發(fā)的J-K觸發(fā)器（帶預(yù)置、清除端、互補(bǔ)輸出）) |
| DM74LS112AN | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs |
| DM74LS11M | Triple 3-Input AND Gate |
| DM74LS11 | Triple 3-Input AND Gate(三3輸入與門) |
| DM74LS11N | Triple 3-Input AND Gate |
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