參數(shù)資料
型號： DK-DEV-2AGX125N
廠商： Altera
文件頁數(shù)： 77/90頁
文件大?。?/td> 0K
描述： KIT DEV ARRIA II GX FPGA 2AGX125
產(chǎn)品培訓模塊： Arria II GX FPGA
Three Reasons to Use FPGA's in Industrial Designs
特色產(chǎn)品： Arria? II GX FPGA Development Kit
標準包裝： 1
系列： Arria II GX
類型： FPGA
適用于相關(guān)產(chǎn)品： EP2AGX125EF35
所含物品： 板，線纜，CD，DVD，電源
產(chǎn)品目錄頁面： 605 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： 544-2599-5-ND - IC ARRIA II GX 125K 1152FBG
544-2598-5-ND - IC ARRIA II GX 125K 1152FBG
544-2597-5-ND - IC ARRIA II GX 125K 1152FBG
其它名稱： 544-2600
Chapter 1: Device Datasheet for Arria II Devices
1–71
Switching Characteristics
December 2013
Altera Corporation
Table 1–63 lists the memory output clock jitter specifications for Arria II GZ devices.
Duty Cycle Distortion (DCD) Specifications
Table 1–64 lists the worst-case DCD specifications for Arria II GX devices.
Table 1–65 lists the worst-case DCD specifications for Arria II GZ devices.
Table 1–63. Memory Output Clock Jitter Specification for Arria II GZ Devices (Note 1), (2), (3)
Parameter
Clock
Network
Symbol
–3
–4
Unit
Min
Max
Min
Max
Clock period jitter
Regional
t
JIT(per)
-55
55
-55
55
ps
Cycle-to-cycle period jitter
Regional
t
JIT(cc)
-110
110
-110
110
ps
Duty cycle jitter
Regional
t
JIT(duty)
-82.5
82.5
-82.5
82.5
ps
Clock period jitter
Global
t
JIT(per)
-82.5
82.5
-82.5
82.5
ps
Cycle-to-cycle period jitter
Global
t
JIT(cc)
-165
165
-165
165
ps
Duty cycle jitter
Global
t
JIT(duty)
-90
90
-90
90
ps
Notes to Table 1–63:
(1) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 SDRAM standard.
(2) The clock jitter specification applies to memory output clock pins generated using differential signal-splitter and DDIO circuits clocked by a
PLL output routed on a regional or global clock network as specified. Altera recommends using regional clock networks whenever possible.
(3) The memory output clock jitter stated in Table 1–63 is applicable when an input jitter of 30 ps is applied.
Table 1–64. Duty Cycle Distortion on I/O Pins for Arria II GX Devices (Note 1)
Symbol
C4
I3, C5, I5
C6
Unit
Min
Max
Min
Max
Min
Max
Output Duty Cycle
45
55
45
55
45
55
%
Note to Table 1–64:
(1) The DCD specification applies to clock outputs from the PLL, global clock tree, IOE driving dedicated, and general
purpose I/O pins.
Table 1–65. Duty Cycle Distortion on I/O Pins for Arria II GZ Devices (Note 1)
Symbol
C3, I3
C4, I4
Unit
Min
Max
Min
Max
Output Duty Cycle
45
55
45
55
%
Note to Table 1–65:
(1) The DCD specification applies to clock outputs from the PLL, global clock tree, IOE driving dedicated, and general
purpose I/O pins.
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