參數(shù)資料
型號(hào)： DK-DEV-2AGX125N
廠商： Altera
文件頁(yè)數(shù)： 57/90頁(yè)
文件大?。?/td> 0K
描述： KIT DEV ARRIA II GX FPGA 2AGX125
產(chǎn)品培訓(xùn)模塊： Arria II GX FPGA
Three Reasons to Use FPGA's in Industrial Designs
特色產(chǎn)品： Arria? II GX FPGA Development Kit
標(biāo)準(zhǔn)包裝： 1
系列： Arria II GX
類型： FPGA
適用于相關(guān)產(chǎn)品： EP2AGX125EF35
所含物品： 板，線纜，CD，DVD，電源
產(chǎn)品目錄頁(yè)面： 605 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： 544-2599-5-ND - IC ARRIA II GX 125K 1152FBG
544-2598-5-ND - IC ARRIA II GX 125K 1152FBG
544-2597-5-ND - IC ARRIA II GX 125K 1152FBG
其它名稱： 544-2600
1–52
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
December 2013
Altera Corporation
OBSAI Receiver Jitter Tolerance (15)
Deterministic jitter tolerance at
768 Mbps, 1536 Mbps, and
3072 Mbps
Pattern = CJPAT
> 0.37
UI
Combined deterministic and
random jitter tolerance at 768
Mbps, 1536 Mbps, and 3072
Mbps
Pattern = CJPAT
> 0.55
UI
Sinusoidal jitter tolerance at 768
Mbps
Jitter frequency = 5.4 KHz
Pattern = CJPAT
> 8.5
UI
Jitter frequency = 460 MHz to 20
MHz
Pattern = CJPAT
> 0.1
UI
Sinusoidal jitter tolerance at
1536 Mbps
Jitter frequency = 10.9 KHz
Pattern = CJPAT
> 8.5
UI
Jitter frequency = 921.6 MHz to 20
MHz
Pattern = CJPAT
> 0.1
UI
Sinusoidal jitter tolerance at
3072 Mbps
Jitter frequency = 21.8 KHz
Pattern = CJPAT
> 8.5
UI
Jitter frequency = 1843.2 MHz to
20 MHz
Pattern = CJPAT
> 0.1
UI
Notes to Table 1–41:
(1) Dedicated refclk pins were used to drive the input reference clocks.
(2) The jitter numbers are valid for the stated conditions only.
(3) The jitter numbers for SONET/SDH are compliant to the GR-253-CORE Issue 3 Specification.
(4) The jitter numbers for Fibre Channel are compliant to the FC-PI-4 Specification revision 6.10.
(5) The Fibre Channel transmitter jitter generation numbers are compliant to the specification at the
T inter operability point.
(6) The Fibre Channel receiver jitter tolerance numbers are compliant to the specification at the
R interpretability point.
(7) The jitter numbers for XAUI are compliant to the IEEE802.3ae-2002 Specification.
(8) The jitter numbers for PCIe are compliant to the PCIe Base Specification 2.0.
(9) Arria II GZ PCIe receivers are compliant to this specification provided the VTX-CM-DC-ACTIVEIDLE-DELTA of the upstream transmitter is less than 50 mV.
(10) The jitter numbers for SRIO are compliant to the RapidIO Specification 1.3.
(11) The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification.
(12) The HD-SDI and 3G-SDI jitter numbers are compliant to the SMPTE292M and SMPTE424M Specifications.
(13) The jitter numbers for Serial Attached SCSI (SAS) are compliant to the SAS-2.1 Specification.
(14) The jitter numbers for CPRI are compliant to the CPRI Specification V3.0.
(15) The jitter numbers for OBSAI are compliant to the OBSAI RP3 Specification V4.1.
Table 1–41. Transceiver Block Jitter Specifications for Arria II GZ Devices (Note 1), (2) (Part 7 of 7)
Symbol/
Description
Conditions
–C3 and –I3
–C4 and –I4
Unit
Min
Typ
Max
Min
Typ
Max
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