參數(shù)資料
型號(hào): DDC118IRTCT
英文描述: Octal Current Input 20-Bit Analog-To-Digital Converter
中文描述: 八路電流輸入20位模擬數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù): 26/30頁(yè)
文件大小: 384K
代理商: DDC118IRTCT
""#
SBAS325A JUNE 2004 REVISED JUNE 2005
www.ti.com
26
POWER-UP SEQUENCING
Prior to power-up, all digital and analog inputs must be low.
After the power supplies have settled, release RESET
after time t
32
. (See Figure 28 and Table 12.) Wait for time
t
33
to begin applying the digital signals CONV and CLK.
The first CONV pulse will complete the release state and
begin integration.
LAYOUT
POWER SUPPLIES AND GROUNDING
Both AVDD and DVDD should be as quiet as possible. It
is particularly important to eliminate noise from AVDD that
is non-synchronous with the DDC118 operation. Figure 27
illustrates two acceptable ways to supply power to the
DDC118. The first case shows two separate +5V supplies
for AVDD and DVDD. In this case, each +5V supply of the
DDC118 should be bypassed with 10
μ
F solid tantalum
capacitors and 0.1
μ
F ceramic capacitors. The second
case shows the DVDD power supply derived from the
AVDD supply with a < 10
isolation resistor. In both cases,
the 0.1
μ
F capacitors should be placed as close to the
DDC118 package as possible. It is recommended that
both the analog and digital grounds (AGND and DGND) be
connected to a single ground plane on the printed circuit
board (PCB).
THERMAL PAD
It is strongly recommended that the thermal pad on the
DDC118 be connected to ground on the PCB. No PCB
traces should be routed underneath the thermal pad.
DDC118
0.1
μ
F
< 10
10
μ
F
+5V
One +5V Supply
AVDD
DVDD
AVDD
DVDD
AGND
DGND
AGND
DGND
DDC118
0.1
μ
F
0.1
μ
F
0.1
μ
F
10
μ
F
VA
Separate Supplies
10
μ
F
VD
Figure 27. Power-Supply Connection Options
Release State
Start Integration
AVDD
DVDD
CONV
RESET
CLK
t
33
Integrate Side B
t
34
t
32
Figure 28. Timing Diagram at Power-Up of the DDC118
Table 12. Timing for the DDC118 Power-Up Sequence
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t32
t33
t34
Power Supplies Settled to RESET Release
10
ms
RESET Release to CONV, CLK Begin
50
μ
s
First CONV Pulse Width
50
μ
s
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