參數(shù)資料
型號: DD28F032SA
廠商: Intel Corp.
英文描述: 32-Mbit (2 Mbit x 16,4 Mbit x 8) FlashFile Memory(32-M位 (2 M位 x 16,4 M位 x 8) FlashFile存儲器)
中文描述: 32兆位(2兆x 16.4兆位× 8)FlashFile內(nèi)存(32米位(2米位x 16,4 M位× 8)FlashFile存儲器)
文件頁數(shù): 36/49頁
文件大小: 736K
代理商: DD28F032SA
DD28F032SA
E
36
SEE NEW DESIGN RECOMMENDATIONS
V
V
WE# (W)
OE# (G)
RP# (P)
VPP
CEx # (E)
(V)
DEEP
POWER-DOWN
IH
IL
V
V
IH
IL
V
V
IH
IL
ADDRESSES (A)
tAVAV
tWHAX
tWHEH
ELWL
t
tWHDX
WHWL
t
V
V
IH
IL
tWLWH
tDVWH
VIH
IL
V
VIH
VIL
PHWL
t
HIGH Z
IN
D
DIN
IN
A
t
tQVVL
DIN
IL
V
IH
V
PPH
V
PPL
V
tVPWH
READ EXTENDED
STATUS REGISTER DATA
DATA (D/Q)
WHQV1,2
WRITE DATA-WRITE OR
ERASE SETUP COMMAND
WRITE VALID ADDRESS
& DATA (DATA-WRITE) OR
ERASE CONFIRM COMMAND
AUTOMATED DATA-WRITE
OR ERASE DELAY
V
V
RY/BY# (R)
tWHRL
tWHGL
OH
OL
V
VIH
IL
ADDRESSES (A)
tAVAV
AVWH
t
tWHAX
IN
A
READ COMPATIBLE
STATUS REGISTER DATA
DIN
WRITE READ EXTENDED
REGISTER COMMAND
A=RA
NOTE 1
NOTE 2
NOTE 3
NOTE 4
DOUT
AVWH
t
tRHPL
tGHWL
NOTE 5
0490-14
NOTES:
1. This address string depicts data program/block erase cycles with corresponding verification via ESRD.
2. This address string depicts data program/block erase cycles with corresponding verification via CSRD.
3. This cycle is invalid when using CSRD for verification during data program/block erase operations.
4. For 28F016SA No. 1: CE
X
# is defined as the latter of CE
0
# or CE
1
# going low, or the first of CE
0
# or CE
1
# going high.
For 28F016SA No. 2: CE
X
# is defined as the latter of CE
0
# or CE
2
# going low, or the first of CE
0
# or CE
2
# going high
5. RP# low transition is only to show t
RHPL
; not valid for above Read and Program cycles.
Figure 14. AC Waveforms for Command Write Operations
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