參數(shù)資料
型號(hào): DD28F032SA-070
廠商: INTEL CORP
元件分類: DRAM
英文描述: 32-MBIT (2 MBIT X 16, 4 MBIT X 8) FlashFile⑩ MEMORY
中文描述: 4M X 8 FLASH 12V PROM, 70 ns, PDSO56
封裝: 14 X 20 MM, 1.20 MM HEIGHT, TSOP-56
文件頁數(shù): 8/49頁
文件大小: 1402K
代理商: DD28F032SA-070
DD28F032SA
E
8
2.1 Lead Descriptions
Symbol
A
0
Type
INPUT
Name and Function
BYTE-SELECT ADDRESS:
Selects between high and low byte when
device is in x8 mode. This address is latched in x8 data programs. Not
used in x16 mode (i.e., the A
0
input buffer is turned off when BYTE# is
high).
WORD-SELECT ADDRESSES:
Select a word within one 64-Kbyte block.
A
6-15
selects 1 of 1024 rows, and A
1-5
selects 16 of 512 columns. These
addresses are latched during data programs.
BLOCK-SELECT ADDRESSES:
Select 1 of 32 erase blocks in each of
the two 28F016SAs. These addresses are latched during data programs,
block erase and lock block operations.
LOW-BYTE DATA BUS:
Inputs data and commands during CUI write
cycles. Outputs array, buffer, identifier or status data in the appropriate
read mode. Floated when the chip is de-selected or the outputs are
disabled.
HIGH-BYTE DATA BUS:
Inputs data during x16 data program
operations. Outputs array, buffer or identifier data in the appropriate read
mode; not used for Status Register reads. Floated when the chip is de-
selected or the outputs are disabled.
CHIP ENABLE INPUTS
: Activate the device’s control logic, input buffers,
decoders and sense amplifiers. CE
0
#/CE
1
# enable/disable the first
28F016SA (16 Mbit No. 1) while CE
0
#/CE
2
# enable/disable the second
28F016SA (16 Mbit No. 2). CE
0
# active low enables chip operation while
CE
1
# or CE
2
# select between the first and second device, respectively
CE
1
# and CE
2
# must not be active low simultaneously. Reference Table
3.0.
RESET/POWER-DOWN:
RP# low places the device in a deep power-
down state. All circuits that burn static power, even those circuits enabled
in standby mode, are turned off. When returning from deep power-down,
a recovery time is required to allow these circuits to power-up.
When RP# goes low, any current or pending WSM operation(s) are
terminated, and the device is reset. All Status Registers return to ready
(with all status flags cleared).
OUTPUT ENABLE:
Gates device data through the output buffers when
low. The outputs float to tri-state off when OE# is high.
NOTE:
CEx# overrides OE#, and OE# overrides WE#.
WRITE ENABLE:
Controls
access to the CUI, Page Buffers, Data Queue
Registers and Address Queue Latches. WE# is active low, and latches
both address and data (command or array) on its rising edge.
READY/BUSY:
Indicates status of the internal WSM. When low, it
indicates that the WSM is busy performing an operation. RY/BY# high
indicates that the WSM is ready for new operations (or WSM has
completed all pending operations), or block erase is suspended, or the
device is in deep power-down mode. This output is always active (i.e., not
floated to tri-state off when OE# or CE
0
#/CE
1
#/CE
2
# are high), except if a
RY/BY#
Pin Disable command is issued.
A
1
–A
15
INPUT
A
16
–A
20
INPUT
DQ
0
–DQ
7
INPUT/OUTPUT
DQ
8
–DQ
15
INPUT/OUTPUT
CE
0
#
CE
X
# =
CE
1
# or
CE
2
#
INPUT
RP#
INPUT
OE#
INPUT
WE#
INPUT
RY/BY#
OPEN DRAIN
OUTPUT
相關(guān)PDF資料
PDF描述
DD28F032SA-080 32-MBIT (2 MBIT X 16, 4 MBIT X 8) FlashFile⑩ MEMORY
DD28F032SA-100 32-MBIT (2 MBIT X 16, 4 MBIT X 8) FlashFile MEMORY
DD28F032SA-150 32-MBIT (2 MBIT X 16, 4 MBIT X 8) FlashFile⑩ MEMORY
DD28F032SA100 x8/x16 Flash EEPROM
DD28F032SA70 x8/x16 Flash EEPROM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DD28F032SA-080 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:32-MBIT (2 MBIT X 16, 4 MBIT X 8) FlashFile⑩ MEMORY
DD28F032SA100 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8/x16 Flash EEPROM
DD28F032SA-100 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:32-MBIT (2 MBIT X 16, 4 MBIT X 8) FlashFile⑩ MEMORY
DD28F032SA-150 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:32-MBIT (2 MBIT X 16, 4 MBIT X 8) FlashFile⑩ MEMORY
DD28F032SA70 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8/x16 Flash EEPROM