FUNCTIONAL BLOCK DIAGRA " />
參數(shù)資料
型號(hào)： DC178A
廠商： Linear Technology
文件頁(yè)數(shù)： 27/28頁(yè)
文件大?。?/td> 0K
描述： BOARD SAR ADC LTC1418
設(shè)計(jì)資源： DC178A Design File
DC178A Schematic
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 14
采樣率（每秒）： 200k
數(shù)據(jù)接口： 串行，并聯(lián)
輸入范圍： ±2.048 V
已用 IC / 零件： LTC1418
已供物品： 板
相關(guān)產(chǎn)品： LTC1418IG#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP
LTC1418AIG#TRPBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP
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LTC1418CG#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP
LTC1418ACG#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP
LTC1418AIG#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP
更多...
8
LTC1418
FUNCTIONAL BLOCK DIAGRA
UU
W
14-BIT CAPACITIVE DAC
COMP
REF AMP
2.5V REF
8k
REFCOMP
4.096V
2.5V
CSAMPLE
D13
D0
BUSY
CONTROL LOGIC
D2/(CLKOUT)
INTERNAL
CLOCK
SHDN
D0 (EXT/INT)
D4 (EXTCLKIN)
CONVST RD CS
ZEROING SWITCHES
D1/(DOUT)
NOTE: PIN NAMES IN PARENTHESES
REFER TO SERIAL MODE
D3/(SCLK)
VDD: 5V
VSS: 0V FOR UNIPOLAR MODE
– 5V FOR BIPOLAR MODE
AIN
+
AIN
–
VREF
AGND
DGND
14
1418 BD
+
–
SUCCESSIVE APPROXIMATION
REGISTER
SHIFT
REGISTER
SER/PAR
MUX
APPLICATIONS INFORMATION
WU
U
CONVERSION DETAILS
The LTC1418 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 14-bit parallel or serial output. The ADC
is complete with a precision reference and an internal
clock. The control logic provides easy interface to micro-
processors and DSPs (please refer to Digital Interface
section for the data format).
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion the successive
approximation register (SAR) is reset. Once a conversion
cycle has begun it cannot be restarted.
During the conversion, the internal differential 14-bit
capacitive DAC output is sequenced by the SAR from the
most significant bit (MSB) to the least significant bit (LSB).
1418 F01
OUTPUT
LATCH
SAR
CDAC
+
CDAC
–
VDAC
–
VDAC
+
–
+
COMP
D13
D0
14
HOLD
AIN
+
AIN
–
ZEROING SWITCHES
CSAMPLE
–
CSAMPLE
+
HOLD
SAMPLE
Figure 1. Simplified Block Diagram
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