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參數(shù)資料
| 型號(hào)： | DC178A |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 26/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD SAR ADC LTC1418 |
| 設(shè)計(jì)資源： | DC178A Design File DC178A Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 輸入范圍： | ±2.048 V |
| 已用 IC / 零件： | LTC1418 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | LTC1418IG#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418AIG#TRPBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418CG#TRPBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418ACG#TRPBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418IG#TRPBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418CN#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28-DIP LTC1418IN#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28-DIP LTC1418CG#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418ACG#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418AIG#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP 更多... |
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7
LTC1418
PIN FUNCTIONS
UU
U
AIN
+ (Pin 1): Positive Analog Input.
AIN
– (Pin 2): Negative Analog Input.
VREF (Pin 3): 2.50V Reference Output. Bypass to AGND
with 1
F.
REFCOMP (Pin 4): 4.096V Reference Bypass Pin.
Bypass to AGND with 10
F tantalum in parallel with 0.1F
ceramic.
AGND (Pin 5): Analog Ground.
D13 to D6 (Pins 6 to 13): Three-State Data Outputs
(Parallel). D13 is the most significant bit.
DGND (Pin 14): Digital Ground for Internal Logic. Tie to
AGND.
D5 (Pin 15): Three-State Data Output (Parallel).
D4 (EXTCLKIN) (Pin 16): Three-State Data Output
(Parallel). Conversion clock input (serial) when Pin 20
(EXT/INT) is tied high.
D3 (SCLK) (Pin 17): Three-State Data Output (Parallel).
Data clock input (serial).
D2 (CLKOUT) (Pin 18): Three-State Data Output (Parallel).
Conversion clock output (serial).
D1 (DOUT) (Pin 19): Three-State Data Output (Parallel).
Serial data output (serial).
D0 (EXT/INT) (Pin 20): Three-State Data Output (Parallel).
Conversion clock selector (serial). An input low enables
the internal conversion clock. An input high indicates an
external conversion clock will be assigned to Pin 16
(EXTCLKIN).
SER/PAR (Pin 21): Data Output Mode.
SHDN (Pin 22): Power Shutdown Input. Low selects
shutdown. Shutdown mode selected by CS. CS = 0 for nap
mode and CS = 1 for sleep mode.
RD (Pin 23): Read Input. This enables the output drivers
when CS is low.
CONVST (Pin 24): Conversion Start Signal. This active low
signal starts a conversion on its falling edge.
CS (Pin 25): Chip Select. This input must be low for the
ADC to recognize the CONVST and RD inputs. CS also sets
the shutdown mode when SHDN goes low. CS and SHDN
low select the quick wake-up nap mode. CS high and
SHDN low select sleep mode.
BUSY (Pin 26): The BUSY Output Shows the Converter
Status. It is low when a conversion is in progress.
VSS (Pin 27): Negative Supply, –5V for Bipolar Operation.
Bypass to AGND with 10
F tantalum in parallel with 0.1F
ceramic. Analog ground for unipolar operation.
VDD (Pin 28): 5V Positive Supply. Bypass to AGND with
10
F tantalum in parallel with 0.1F ceramic.
TEST CIRCUITS
1k
CL
DBN
DGND
A) HI-Z TO VOH AND VOL TO VOH
CL
DBN
1k
5V
B) HI-Z TO VOL AND VOH TO VOL
DGND
1418 TC01
Load Circuits for Access Timing
Load Circuits for Output Float Delay
1k
30pF
DBN
A) VOH TO HI-Z
30pF
DBN
1k
5V
B) VOL TO HI-Z
1418 TC02
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