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參數(shù)資料
| 型號： | DC178A |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 18/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD SAR ADC LTC1418 |
| 設(shè)計資源： | DC178A Design File DC178A Schematic |
| 標(biāo)準包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 輸入范圍： | ±2.048 V |
| 已用 IC / 零件： | LTC1418 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | LTC1418IG#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418AIG#TRPBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418CG#TRPBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418ACG#TRPBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418IG#TRPBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418CN#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28-DIP LTC1418IN#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28-DIP LTC1418CG#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418ACG#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418AIG#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP 更多... |
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25
LTC1418
APPLICATIONS INFORMATION
WU
U
also allows operation when the SCLK frequency is very low
(less than 30kHz). To select the internal conversion clock
tie EXT/INT low. The external SCLK is applied to SCLK. RD
can be used to gate the external SCLK, such that data will
clock only after RD goes low and to three-state DOUT after
data transfer. If more than 16 SCLKs are provided, more
zeros will be filled in after the data word indefinitely.
LTC1418
BUSY
CONVST
RD
EXTCLKIN
SCLK
EXT/INT
DOUT
CS
5V
25
16
24
23
17
26
19
20
1418 F25a
P OR DSP
CLKOUT
INT
C0
SCK
MISO
t5
t6
123456789 10 11 12 13 14 15 16
CS = 0, EXT/INT = 5
CONVST
EXTCLKIN
t13
tdEXTCLKIN
t8
HOLD
SAMPLE
t9
t7
t11
BUSY
SCLK
RD
123456789 10 11 12 13 14 15 16
1
2
34
12 11 10 987654321
0
FILL
ZEROS
D13
Hi-Z
DATA N
Hi-Z
(SAMPLE N)
DOUT
tCONV
t10
1418 F25b
D11
D12
CAPTURE ON
RISING CLOCK
D13
t15
t14
SCLK
VIL
VOH
VOL
DOUT
CAPTURE ON
FALLING CLOCK
tLSCLK
tHSCLK
Figure 25. External Conversion Clock Selected. Data Transferred After Conversion
Using an External SCLK. BUSY
↑ Indicates End of Conversion
Using External Conversion Clock and External Data
Clock. In Figure 25, data is also output after each conver-
sion is completed and before the next conversion is
started. An external clock is used for the conversion clock
and either another or the same external clock is used for
the SCLK. This mode is identical to Figure 24 except that
an external clock is used for the conversion. This mode
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