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參數(shù)資料
| 型號： | DC1684A-B |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 15/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD DAC LTC2752 |
| 軟件下載： | QuikEval System |
| 設(shè)計資源： | DC1684A Design File DC1684A Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuikEval™, SoftSpan™ |
| DAC 的數(shù)量： | 2 |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 設(shè)置時間： | 2µs |
| DAC 型： | 電流 |
| 工作溫度： | 0°C ~ 70°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | LTC2752 |
| 相關(guān)產(chǎn)品： | DC590B-ND - BOARD DEMO USB SERIAL CONTROLLER LTC2752BILX#PBF-ND - IC DAC 16BIT DUAL CUR OUT 48LQFP LTC2752AILX#PBF-ND - IC DAC 16BIT DUAL CUR OUT 48LQFP LTC2752BCLX#PBF-ND - IC DAC 16BIT DUAL CUR OUT 48LQFP LTC2752ACLX#PBF-ND - IC DAC 16BIT DUAL CUR OUT 48LQFP |
LTC2752
2752f
in 5V or 10V full-scale systems. However, as the circuit
bandwidths increase, filtering the output of the reference
may be required to minimize output noise.
Grounding
As with any high resolution converter, clean grounding
is important. A low impedance analog ground plane is
necessary, as are star grounding techniques. Keep the
board layer used for star ground continuous to minimize
ground resistances; that is, use the star-ground concept
without using separate star traces. The IOUT2 pins are
of particular concern; INL will be degraded by the code
dependent currents carried by the IOUT2XF and IOUT2XS
pins if voltage drops to ground are allowed to develop.
applicaTions inForMaTion
The best strategy here is to tie the pins to the star ground
plane by multiple vias located directly underneath the part.
Alternatively, the pins may be routed to the star ground
point if necessary; join the force and sense pins together
at the part and route one trace for each channel of no more
than 120 squares of 1oz. copper.
In the rare case in which neither of these alternatives is
practicable, a force/sense amplifier should be used as a
ground buffer (see Typical Applications). Note, however,
that the voltage offset of the ground buffer amp directly
contributes to the effects on accuracy specified in Table
5 under VOS1. The combined effects of the offsets can be
calculated by substituting the total offset from IOUT1X to
IOUT2XS for VOS1 in the equations.
Figure 5. Optional Circuits for Driving IOUT2 from GND with a Force/Sense Amplifier
–
+
–
+
1/2 LT1469
DAC A
LTC2752
VREF
5V
2
1
3
44
45, 46
47, 48
5, 6
4
3
1
1, 2
IOUT1A
15pF
IOUT2A
RFBA
VOSADJA
REFA
RCOMA
RINA
ROFSA
VOUTA
8, 9
43
2752 F05
150pF
3
2
DAC B
–
+
GEADJA
–
+
6
9
8
1
2
3
IOUT2AF
IOUT2AS
2
3
*SCHOTTKY BARRIER DIODE
ZETEX*
BAT54S
LT1012
1000pF
ALTERNATE AMPLIFIER FOR OPTIMUM SETTLING TIME PERFORMANCE
6
9
1
2 3
8
–
+
LT1468
3
ZETEX
BAT54S
2
200
IOUT2AS
IOUT2AF
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