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參數(shù)資料
| 型號： | DC1485A |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD DAC LTC2757 |
| 軟件下載： | QuikEval System |
| 設(shè)計資源： | DC1485A Design Files DC1485A Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuikEval™, SoftSpan™ |
| DAC 的數(shù)量： | 1 |
| 位數(shù)： | 18 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 設(shè)置時間： | 2.1µs |
| DAC 型： | 電流 |
| 已供物品： | 板 |
| 已用 IC / 零件： | LTC2757 |
| 相關(guān)產(chǎn)品： | DC590B-ND - BOARD DEMO USB SERIAL CONTROLLER LTC2757BCLX#PBF-ND - IC DAC 18BIT PAR 48LQFP LTC2757ACLX#PBF-ND - IC DAC 18BIT PAR 48LQFP LTC2757BILX#PBF-ND - IC DAC 18BIT PAR 48LQFP LTC2757AILX#PBF-ND - IC DAC 18BIT PAR 48LQFP |
LTC2757
12
2757f
Figure 1. Conguring the LTC2757 for
Single-Span Operation (±10V Range)
OPERATION
The most common readback task is to check the contents
of an Input register after writing to it, and before updating
the new data to the DAC register. To do this, hold UPD low
and assert READ high. The contents of the selected port’s
Input register are output to its I/O pins.
To read back the contents of a DAC register, hold UPD low
and assert READ high, then bring UPD high to select the
DAC register. The contents of the selected DAC register are
output by the selected port’s I/O pins. Note: if no update is
desired after the readback operation, UPD must be returned
low before bringing READ low, otherwise the UPD pin will
revert to its primary function and update the DAC.
Table 2. Span Codes
S2
S1
S0
SPAN
0
Unipolar 0V to 5V
0
1
Unipolar 0V to 10V
0
1
0
Bipolar –5V to 5V
0
1
Bipolar –10V to 10V
1
0
Bipolar –2.5V to 2.5V
1
0
1
Bipolar –2.5V to 7.5V
Codes not shown are reserved and should not be used.
Readback
The contents of any one of the four interface registers can
be read back from the I/O ports by using the READ pin in
conjunction with the D/S and UPD pins.
The I/O pins and registers are grouped into two ports—Data
and Span. The Data I/O port consists of pins D0-D17, and
the Span I/O port consists of pins S0, S1 and S2.
Each I/O port has one dedicated Input register and one
dedicated DAC register. The register structure is shown
in the Block Diagram.
A Readback operation is initiated by asserting READ to
logic high after selecting the desired I/O port.
Select the I/O port (Data or Span) to be read back with
the D/S pin. The selected I/O port’s pins become logic
outputs during readback, while the unselected I/O port’s
pins remain high-impedance digital inputs.
With the I/O port selected, assert READ high and select
the desired Input or DAC register using the UPD pin. Note
that UPD is a two function pin—the Update function is only
available when READ is low. If READ is high, the Update
function is disabled and the UPD pin instead functions
as a register selector, selecting an Input or DAC register
for readback. Table 1 shows the readback functions for
the LTC2757.
Table 1. Write, Update and Read Functions
READ D/S
WR UPD
SPAN I/O
DATA I/O
0
-
Write to Input Register
0
1
-
Write/Update
(Transparent)
00
1
0
-
0
1
Update DAC Register
0
1
0
Write to Input Register
-
0
1
0
1
Write/Update
(Transparent)
-
01
1
0
-
0
1
Update DAC register
Update DAC Register
1
0
X
0
-
Read Input Register
1
0
X
1
-
Read DAC Register
1
X
0
Read Input Register
-
1
X
1
Read DAC Register
-
X = Don’t Care
LTC2757
M-SPAN
S2
S1
S0
D/S
VDD
2757 F01
WR UPD READ
DATA I/O
18
VDD
System Offset and Gain Adjustments
Many systems require compensation for overall system
offset. This may be an order of magnitude or more greater
than the offset of the LTC2757, which is so low as to be
dominated by external output amplier errors even when
using the most precise op amps.
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