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參數(shù)資料
| 型號： | DC1485A |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 16/20頁 |
| 文件大小： | 0K |
| 描述： | BOARD DAC LTC2757 |
| 軟件下載： | QuikEval System |
| 設(shè)計(jì)資源： | DC1485A Design Files DC1485A Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuikEval™, SoftSpan™ |
| DAC 的數(shù)量： | 1 |
| 位數(shù)： | 18 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 設(shè)置時(shí)間： | 2.1µs |
| DAC 型： | 電流 |
| 已供物品： | 板 |
| 已用 IC / 零件： | LTC2757 |
| 相關(guān)產(chǎn)品： | DC590B-ND - BOARD DEMO USB SERIAL CONTROLLER LTC2757BCLX#PBF-ND - IC DAC 18BIT PAR 48LQFP LTC2757ACLX#PBF-ND - IC DAC 18BIT PAR 48LQFP LTC2757BILX#PBF-ND - IC DAC 18BIT PAR 48LQFP LTC2757AILX#PBF-ND - IC DAC 18BIT PAR 48LQFP |
LTC2757
5
2757f
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
CLR Timing
t25
CLR Pulse Width Low
l
20
ns
VDD = 2.7V to 3.3V
Write and Update Timing
t1
I/O Valid to WR Rising Edge Set-Up
l
18
ns
t2
I/O Valid to WR Rising Edge Hold
l
18
ns
t3
WR Pulse Width
l
30
ns
t4
UPD Pulse Width
l
30
ns
t5
UPD Falling Edge to WR Falling Edge
No Data Shoot-Through
l
0ns
t6
WR Rising Edge to UPD Rising Edge
(Note 12)
l
0ns
t7
D/S Valid to WR Falling Edge Set-Up Time
l
18
ns
t8
WR Rising Edge to D/S Valid Hold Time
l
18
ns
Readback Timing
t13
WR Rising Edge to Read Rising Edge
l
18
ns
t14
Read Falling Edge to WR Falling Edge
(Note 12)
l
40
ns
t15
Read Rising Edge to I/O Propagation Delay
CL = 10pF
l
48
ns
t17
UPD Valid to I/O Propagation Delay
CL = 10pF
l
48
ns
t18
D/S Valid to Read Rising Edge
(Note 12)
l
18
ns
t19
Read Rising Edge to UPD Rising Edge
No Update
l
9ns
t20
UPD Falling Edge to Read Falling Edge
No Update
l
9ns
t22
READ Falling Edge to UPD Rising Edge
(Note 12)
l
18
ns
t23
I/O Bus Hi-Z to Read Rising Edge
(Note 12)
l
0ns
t24
Read Falling Edge to I/O Bus Active
(Note 12)
l
40
ns
CLR Timing
t25
CLR Pulse Width Low
l
30
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Continuous operation above the specied maximum operating
junction temperature may impair device reliability.
Note 3: Temperature Coefcient is calculated by dividing the maximum
change in the parameter by the specied temperature range.
Note 4: R1 is measured from RIN to RCOM; R2 is measured from REF to
RCOM.
Note 5: Parallel combination of the resistances from REF to IOUT1 and from
REF to IOUT2. DAC input resistance is independent of code.
Note 6: Because of the proprietary SoftSpan switching architecture, the
measured resistance looking into each of the specied pins is constant for
all output ranges if the IOUT1 and IOUT2 pins are held at ground.
TIMING CHARACTERISTICS V
DD = 5V, V(RIN) = 5V unless otherwise specied. The l denotes specications that
apply over the full operating temperature range, otherwise specications are at TA = 25°C.
Note 7: Using LT1468 with CFEEDBACK = 27pF. A ±0.0004% settling time
of 1.8μs can be achieved by optimizing the time constant on an individual
basis. See Application Note 120,
1ppm Settling Time Measurement for a
Monolithic 18-Bit DAC.
Note 8: Measured at the major carry transition, 0V to 5V range. Output
amplier: LT1468; CFB = 50pF.
Note 9: Zero-code to full-code transition; REF = 0V. Falling transition is
similar or better.
Note 10: REF = 6VRMS at 1kHz. 0V to 5V range. DAC code = FS. Output
amplier = LT1468.
Note 11: Calculation from Vn = √4kTRB, where k = 1.38E-23 J/°K
(Boltzmann constant), R = resistance (
Ω), T = temperature (°K), and B =
bandwidth (Hz).
Note 12: Guaranteed by design. Not production tested.
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