fEOSC External Oscillator Frequency Rang" />
參數(shù)資料
型號(hào)： DC1010A-B
廠商： Linear Technology
文件頁(yè)數(shù)： 20/24頁(yè)
文件大小： 0K
描述： BOARD DELTA SIGMA ADC LTC2489
軟件下載： QuikEval System
設(shè)計(jì)資源： DC1010A Design File
DC1010A Schematic
標(biāo)準(zhǔn)包裝： 1
系列： Easy Drive™, QuikEval™
ADC 的數(shù)量： 1
位數(shù)： 16
采樣率（每秒）： 7.5
數(shù)據(jù)接口： I²C，串行
已用 IC / 零件： LTC2489
已供物品： 板
相關(guān)產(chǎn)品： LTC2489IDE#TRPBF-ND - IC ADC 16BIT DELTA SIG 14-DFN
LTC2489CDE#TRPBF-ND - IC ADC 16BIT DELTA SIG 14-DFN
LTC2489CDE#PBF-ND - IC ADC 16BIT DELTA SIG 14-DFN
LTC2489IDE#PBF-ND - IC ADC 16BIT DELTA SIG 14-DFN
LTC2489
5
2489fa
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fEOSC
External Oscillator Frequency Range
(Note 16)
l
10
4000
kHz
tHEO
External Oscillator High Period
l
0.125
50
μs
tLEO
External Oscillator Low Period
l
0.125
50
μs
tCONV
Conversion Time
Internal Oscillator
External Oscillator (Note 10)
l
144.1
146.9
41036/fEOSC (in kHz)
149.9
ms
DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fSCL
SCL Clock Frequency
l
0
400
kHz
tHD(STA)
Hold Time (Repeated) Start Condition
l
0.6
μs
tLOW
Low Period of the SCL Pin
l
1.3
μs
tHIGH
High Period of the SCL Pin
l
0.6
μs
tSU(STA)
Set-Up Time for a Repeated Start Condition
l
0.6
μs
tHD(DAT)
Data Hold Time
l
0
0.9
μs
tSU(DAT)
Data Set-Up Time
l
100
ns
tr
Rise Time for SDA Signals
(Note 14)
l
20 + 0.1CB
300
ns
tf
Fall Time for SDA Signals
(Note 14)
l
20 + 0.1CB
300
ns
tSU(STO)
Set-Up Time for Stop Condition
l
0.6
μs
I2C TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3, 15)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 2.7V to 5.5V unless otherwise specified.
VREFCM = VREF/2, FS = 0.5VREF
VIN = IN+ – IN–, VIN(CM) = (IN+ – IN–)/2,
where IN+ and IN– are the selected input channels.
Note 4: Use internal conversion clock or external conversion clock source
with fEOSC = 307.2kHz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: fEOSC = 256kHz ±2% (external oscillator).
Note 8: fEOSC = 307.2kHz ±2% (external oscillator).
Note 9: Simultaneous 50Hz/60Hz (internal oscillator) or fEOSC = 280kHz
±2% (external oscillator).
Note 10: The external oscillator is connected to the fO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 11: The converter uses its internal oscillator.
Note 12: The output noise includes the contribution of the internal
calibration operations.
Note 13: Guaranteed by design and test correlation.
Note 14: CB = capacitance of one bus line in pF (10pF ≤ CB ≤ 400pF).
Note 15: All values refer to VIH(MIN) and VIL(MAX) levels.
Note 16: Refer to Applications Information section for performance versus
data rate graphs.
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