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參數(shù)資料
| 型號： | DAC8420FSZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT QUAD SRL LP 16SOIC |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1,000 |
| 設(shè)置時間： | 8µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 255mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應商設(shè)備封裝： | 16-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電壓，單極；4 電壓，雙極 |
| 采樣率（每秒）： | 125k |
DAC8420
Rev. B | Page 16 of 24
VREFHI INPUT REQUIREMENTS
The DAC8420 utilizes a unique, patented DAC switch driver
circuit that compensates for different supply, reference voltage,
and digital code inputs. This ensures that all DAC ladder switches
are always biased equally, ensuring excellent linearity under all
conditions. Thus, as shown in Table 1, the VREFHI input of the
DAC8420 requires both sourcing and sinking current capabili-
ties from the reference voltage source. Many positive voltage
references are intended as current sources only and offer little
sinking capability. The user should consider references such as
such an application.
POWER-UP SEQUENCE
To prevent a CMOS latch-up condition, power up VDD, VSS,
and GND prior to any reference voltages. The ideal power-up
sequence is GND, VSS, VDD, VREFHI, VREFLO, and digital
inputs. Noncompliance with the power-up sequence over an
extended period can elevate the reference currents and eventually
damage the device. On the other hand, if the noncompliant
power-up sequence condition is as short as a few milliseconds,
the device can resume normal operation without being damaged
once VDD/VSS is powered.
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相關(guān)代理商/技術(shù)參數(shù) |
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| DAC8420FSZ-REEL2 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad 12-Bit Serial Voltage Output DAC |
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| DAC8420QBC | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad 12-Bit Serial Voltage Output DAC |
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| DAC8426AR | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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