參數(shù)資料
型號: DAC1005D750HW
廠商: NXP Semiconductors N.V.
元件分類: 外設(shè)及接口
英文描述: Dual 10-bit DAC, up to 750 Msps; 2x 4x and 8x interpolating
封裝: DAC1005D750HW/C1<SOT638-1 (HTQFP100)|<<http://www.nxp.com/packages/SOT638-1.html<1<Always Pb-free,;DAC1005D750HW/C1<SOT638-1 (HTQFP100)|<<http://www.nxp.com/packages/SOT6
文件頁數(shù): 18/42頁
文件大?。?/td> 353K
代理商: DAC1005D750HW
DAC1005D750
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 June 2011
18 of 42
NXP Semiconductors
DAC1005D750
Dual 10-bit DAC, up to 750 Msps; 4x and 8x interpolating
Table 12.
Default settings are shown highlighted.
Bit
Symbol
Table 13.
Bit
7 to 0
4 to 2 MODULATION[2:0]
R/W
modulation
dual DAC: no modulation
positive upper single sideband
up-conversion
positive lower single sideband up-conversion
negative upper single sideband
up-conversion
negative lower single sideband
up-conversion
interpolation
reserved
4
8
000
001
010
011
100
1 to 0 INTERPOLATION[1:0]
R/W
01
10
11
PLLCFG register (address 02h) bit description
Access Value Description
PLL ON
PLL
PLL OFF
7
PLL_PD
R/W
0
1
-
switched on
switched off
6
-
-
reserved
5
PLL_DIV_PD
R/W
PLL divider
switched on
switched off
PLL divider factor
2
4
8
X
phase shift (f
s
)
0
120
240
clock edge of DAC (f
s
)
normal
inverted
undefined
X
X
Digital clock delay
130 ps
280 ps
430 ps
580 ps
undefined
X
X
X
undefined
X
X
0
1
4 to 3
PLL_DIV[1:0]
R/W
00
01
10
11
2 to 1
DAC_CLK_DELAY[1:0] R/W
00
01
10
0
DAC_CLK_POL
R/W
0
1
FREQNCO_LSB register (address 03h) bit description
Symbol
Access Value Description
FREQ_NCO[7:0]
R/W
-
lower 8 bits for the NCO frequency setting
Table 11.
Default settings are shown highlighted.
Bit
Symbol
TXCFG register (address 01h) bit description
…continued
Access
Value Description
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