參數(shù)資料
型號: DAC1005D750HW
廠商: NXP Semiconductors N.V.
元件分類: 外設(shè)及接口
英文描述: Dual 10-bit DAC, up to 750 Msps; 2x 4x and 8x interpolating
封裝: DAC1005D750HW/C1<SOT638-1 (HTQFP100)|<<http://www.nxp.com/packages/SOT638-1.html<1<Always Pb-free,;DAC1005D750HW/C1<SOT638-1 (HTQFP100)|<<http://www.nxp.com/packages/SOT6
文件頁數(shù): 17/42頁
文件大小: 353K
代理商: DAC1005D750HW
DAC1005D750
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 June 2011
17 of 42
NXP Semiconductors
DAC1005D750
Dual 10-bit DAC, up to 750 Msps; 4x and 8x interpolating
10.2.4
Detailed register descriptions
Please refer to
Table 9
for the register overview and relevant default values. In the
following tables, all the values shown in bold are the default values.
Table 10.
Default settings are shown highlighted.
Bit
Symbol
7
3W_SPI
Table 11.
Default settings are shown highlighted.
Bit
Symbol
7
NCO_ON
COMMon register (address 00h) bit description
Access
R/W
Value Description
serial interface bus type
0
4 wire SPI
1
3 wire SPI
serial interface reset
0
no reset
1
performs a reset on all registers except 00h
data input latch
0
at CLK rising edge
1
at CLK falling edge
-
reserved
input data mode
0
dual port
1
interleaved
coding
6
SPI_RST
R/W
5
CLK_SEL
R/W
4
3
-
MODE_SEL
-
R/W
2
CODING
R/W
0
1
binary
two’s compliment
power-down
disabled
all circuits (digital and analog, except SPI)
are switched off
internal bandgap power-down
power-down disabled
internal bandgap references are switched off
1
IC_PD
R/W
0
1
0
GAP_PD
R/W
0
1
TXCFG register (address 01h) bit description
Access
R/W
Value Description
NCO
0
disabled (the NCO phase is reset to 0)
1
enabled
low-power NCO
0
disabled
1
NCO frequency and phase given by the five
MSBs of the registers 06h and 08h
respectively
x / (sin x) function
0
disabled
1
enabled
6
NCO_LP_SEL
R/W
5
INV_SIN_SEL
R/W
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